SLUS696C June   2006  – February 2019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Standard Serial Communication (SDQ) Timing
    7. 6.7 OTP Programming Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Non-Volatile Memory
      2. 7.3.2 Authentication
      3. 7.3.3 Communication and Power
    4. 7.4 Device Functional Modes
      1. 7.4.1 Profile Command
      2. 7.4.2 Sleep Mode Description
    5. 7.5 Programming
      1. 7.5.1 Communicating with the bq26100 Device
      2. 7.5.2 Memory Descriptions
        1. 7.5.2.1 Non-Volatile OTP Memory
          1. 7.5.2.1.1 General Use – Memory Function Commands 0xF0 (Read) and 0x0F (Write)
          2. 7.5.2.1.2 General Use — Memory Function Commands 0xFA (Read) and 0xAF (Write)
          3. 7.5.2.1.3 Status – Memory Function Commands 0xAA (Read) and 0x55 (Write)
            1. 7.5.2.1.3.1 PAGE LOCK (offset = D431h) [reset = 0h]
              1. Table 5. PAGE LOCK Field Descriptions
        2. 7.5.2.2 Non-Volatile EEPROM Memory
          1. 7.5.2.2.1 General Use – Memory Function Commands 0xE0 (Read) and 0x0E (Write)
      3. 7.5.3 SHA-1 Description
      4. 7.5.4 Key Programming Description
    6. 7.6 Register Maps
      1. 7.6.1 Volatile Register Memory
        1. 7.6.1.1 Message and Digest Registers – Memory Function Command 0xDD (Read) and 0x22 (Write)
        2. 7.6.1.2 Control and Version Registers – Memory Function Command 0x88 (Read) and 0x77 (Write)
          1. 7.6.1.2.1 CTRL Register (address = 0001h) [reset = 1h]
            1. Table 9. Control Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.6.1.2.1 CTRL Register (address = 0001h) [reset = 1h]

Figure 22. Control Register
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
0h 0h 0h 0h 0h 1h 0h 0h

Table 9. Control Register Field Descriptions

Bit Field Type Reset Description
7 PROGK1 R/W 0h

If LOCKK1 is 1 (see Status Register), writing this bit to 1 enables the programming of Device Key 1. Further information about the programming of the keys is found in the SHA-1 section.
6 PROGK0 R/W 0h

If the LOCKK0 bit is 1 (see Status Register), writing this bit to 1 enables the programming of Device Key 0. Further information about the programming of the keys is found in the SHA-1 section.
5 RSVD R/W 0h

These bits are reserved for future use. They should always be written to 0.
4 CLEAR R/W 0h

Writing this bit to 1 clears the message/digest registers. This can be done before the message is written to ensure that all data values are known or after the digest is read to clear the HMAC calculation output. The bq26100 device resets the bit back to 0.
3 RSVD R/W 0h

Reserved
2 POR R/W 1h

This bit is set when the device comes out of a POR condition. The bit can be written to 0 to clear the flag. Writing the bit to 1 has no effect on device operation.
1 DONE R/W 0h

This bit is set when the device completes the HMAC calculation. The host should poll for this bit to determine when the digest is available for reading. This bit is automatically cleared when the AUTH bit is written to 1. This bit is also cleared at POR.
0 AUTH R/W 0h

This bit is set to initiate the HMAC calculation. This bit is automatically cleared when the DONE bit is written to 1.
bq26100 ctr_reg_lus696.gif
1. 16-Bit address is sent with lower 8-bit address followed by higher 8-bit address with least significant bit first.
Figure 23. Control Register Write/Read Flows