ZHCSIU4A September 2018 – August 2019 ADS1284
PRODUCTION DATA.
The ADS1284 is a high-performance analog-to-digital converter (ADC) designed for energy exploration, seismic monitoring, laboratory instrumentation, and other exacting performance applications. The converter provides 31-bit resolution in data rates from 250 SPS to 4000 SPS. See the Functional Block Diagram section for a block diagram of the ADS1284.
The ADS1284 provides two modes of operation, high resolution and low power. The modes offer a tradeoff between power consumption and SNR performance. For most ADC configurations, low-power mode reduces power consumption 6 mW but results in an average 3 dB decrease of SNR. The operating mode is programmed by the MODE register bit (see Figure 71).
The two-channel, differential-input multiplexer allows several measurement configurations:
The input multiplexer is followed by a continuous-time PGA featuring very low noise. The gain of the PGA is programmed by register settings (gains 1 to 64). A external 10-nF C0G capacitor connected to CAPP and CAPN provides the ADC antialias filter.
The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal (VIN = AINP – AINN) against the differential reference (VREF = (VREFP – VREFN) / 2) to yield differential input voltage range = ±2.5 V (PGA = 1). A digital output (MFLAG) indicates the modulator is in overload as a result of an overdrive condition. The modulator digital output data is routed to the digital filter to provide the conversion output data.
The digital filter consists of a variable decimation rate, fifth-order sinc filter, followed by a variable phase, fixed-decimation, finite-impulse response (FIR) low-pass filter with programmable phase. The last filter stage is an adjustable high-pass filter for dc and low frequency signal removal. The output of the digital filter can be taken from the sinc or the FIR filter stages, with the option of the FIR plus high-pass filter stages.
Gain and offset registers scale the output of the digital filter to produce the final output conversion data. The scaling feature can be used for calibration and sensor gain matching.
The SYNC input resets the operation of both the digital filter and the modulator, synchronizing the conversions of multiple ADCs to an external timing event. The SYNC input supports a continuous input mode that accepts an external data frame clock that is locked to the conversion rate. Automatic synchronization occurs when the periods are mismatched.
The RESET input resets the register settings and also restarts the conversion process.
The PWDN input sets the device into power down. Note that register settings are not retained in PWDN mode. Use the STANDBY command for software power down (the quiescent current in standby mode is slightly higher).
Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) increase reliability in high-noise environments. The SPI™-compatible serial interface is used to read conversion data, in addition to reading from and writing to the configuration registers.
The device supports either unipolar (+5 V) or bipolar (±2.5 V) supply operation. The digital supply range 1.8 V to 3.3 V.
An internal subregulator powers the digital core from the DVDD supply. BYPAS (pin 28), is the subregulator output and requires a 1-μF capacitor for noise reduction. Note that the regulated output voltage on BYPAS is not available to drive external circuitry.