SN65EPT22
- Dual 3.3V LVTTL to LVPECL Buffer
- Operating Range
- LVPECL VCC = 3.0 V to 3.6 V With
GND = 0 V
- LVPECL VCC = 3.0 V to 3.6 V With
- Support for Clock Frequencies to 2.0 GHz (typ)
- 420 ps Typical Propagation Delay
- Deterministic HIGH Output Value for Open Input
Conditions - Built-in Temperature Compensation
- Drop in Compatible to MC100ELT23
- PNP Single Ended Inputs for Minimal Loading
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion
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The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
技术文档
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer 数据表 (Rev. B) | PDF | HTML | 2014-11-19 | ||
| 应用手册 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007-10-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
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