SN65EPT23
- Dual 3.3 V Differential LVPECL/LVDS to
LVTTL/LVCMOS Buffer Translator - 24 mA LVTTL Ouputs
- Operating Range
- VCC = 3.0 V to 3.6 V
- GND = 0 V
- Support for Clock Frequencies > 300 MHz
- 2.0 ns Typical Propagation Delay
- Built-in Temperature Compensation
- Drop in Compatible to MC100EPT23
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left open. The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.
技术文档
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 3.3-V ECL Differential Receiver 数据表 (Rev. A) | 2011-1-27 | |||
| 应用手册 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007-10-17 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
订购和质量
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