SN65EPT21
- 1 ns Propagation Delay
- Fmax > 300MHz
- Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
- 24-mA TTL Output
- Built-In Temperature Compensation
- Drop-In Compatible to the MC10EPT21, MC100EPT21
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65EPT21 is a differential PECL-to-TTL translator. It operates on +3.3 V supply and ground only. The device includes circuitry to maintain inputs at Vcc/2 when left open.
The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.
The SN65EPT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 3.3V ECL Differential Receiver 数据表 | 2009-2-10 | |||
| 应用手册 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007-10-17 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
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