LMK03200
- Integrated VCO with Very Low Phase Noise Floor
- Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
- VCO Divider Values of 2 to 8 (All
Divides)
- Bypassable with VCO Mux When Not in 0-delay Mode
- Channel Divider Values of 1, 2 to 510 (Even Divides)
- LVDS and LVPECL Clock Outputs
- Partially Integrated Loop Filter
- Dedicated Divider and Delay Blocks on Each Clock Output
- 0-delay Outputs
- Internal or External Feedback of Output Clock
- Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
- Pin Compatible Family of Clocking Devices
- 3.15 to 3.45 V Operation
- Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
- 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock
All trademarks are the property of their respective owners.
The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO 数据表 (Rev. C) | 2013-4-19 | |||
| 设计指南 | Clock Conditioner Owner's Manual | 2006-11-10 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
CLOCKDESIGNTOOL — Clock Design Tool Software
时钟设计工具软件可帮助选择器件、设计环路滤波器，并进行定时器件解决方案仿真。当您输入所需的输出频率和参考频率（可选）后，该工具就会提供能够满足指定要求的 TI 器件、分频器值，并推荐能够尽可能减少抖动的环路滤波器。
CLOCKDESIGNTOOL 教程视频
我要使用哪一个软件？
产品 | 环路滤波器和器件配置 + 仿真 | 模拟工具 | 器件寄存器编程 |
LMX24xx PLL 系列 | EasyPLL | ||
LMX25xx PLL+VCO 系列 | 时钟设计工具 | ||
LMK 抖动清除器和分配器 |
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州仪器 (TI) 时钟和合成器 (TICS) 专业软件用于对具有以下前缀的产品编号的评估模块 (EVM) 进行编程：CDC、LMK 和 LMX。这些产品包括锁相环和电压控制振荡器 (PLL+VCO)、合成器和时钟器件。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |