DS90CF564
- 20 to 65 MHz Shift Clk Support
- Up to 171 Mbytes/s Bandwidth
- Cable Size is Reduced to Save Cost
- 290 mV Swing LVDS Devices for Low EMI
- Low Power CMOS Design (< 550 mW typ)
- Power-down Mode Saves Power (< 0.25 mW)
- PLL Requires No External Components
- Low Profile 48-Lead TSSOP Package
- Falling Edge Data Strobe
- Compatible with TIA/EIA-644 LVDS Standard
- Single Pixel Per Clock XGA (1024 x 768)
- Supports VGA, SVGA, XGA and Higher
- 1.3 Gbps Throughput
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The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 171 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display(FPD) Link - 65 MHz 数据表 (Rev. E) | 2013-4-17 | |||
| 应用手册 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018-11-9 | ||||
| 应用手册 | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018-6-29 | ||||
| 应用手册 | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017-8-8 | ||||
| 应用手册 | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004-5-15 | ||||
| 应用手册 | AN-1056 STN Application Using FPD-Link | 2004-5-14 | ||||
| 应用手册 | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004-5-14 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |