CDCLVP2102
- Dual 1:2 Differential Buffer
- Two Clock Inputs
- Universal Inputs Can Accept LVPECL,
LVDS, LVCMOS/LVTTL - Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption:
48 mA - Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range - 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Within Bank Output Skew: 10 ps
- LVPECL Reference Voltage, VAC_REF,
Available for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C
to +85°C - Supports 105°C PCB Temperature
(Measured with a Thermal Pad) - Available in 3-mm × 3-mm, 16-Pin
VQFN (RGT) Package - ESD Protection Exceeds 2000 V (HBM)
The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2102 is characterized for operation from –40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. C) | PDF | HTML | 2013-10-25 | ||
| 用户指南 | CDCLVP2102 User's Guide | 2009-7-9 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
CDCLVP2102EVM — CDCLVP2102 评估模块
CDCLVP2102 是一款高性能、低附加相位噪声时钟缓冲器。它具有两个通用输入缓冲器，支持单端或差动时钟输入，并且每个输入可馈给 2 个 LVPECL 输出。该器件还具有片上偏压发生器，它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP2102 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP2102 器件的所有功能进行全面验证。为达到最佳性能，该评估板配备有 50W SMA 连接器和受控良好的 50W 阻抗微带传输线。
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
订购和质量
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