AFE7988
- Quad RF sampling 12-GSPS transmit DACs
- Quad RF sampling 3-GSPS receive ADCs
- Dual RF sampling 3-GSPS feedback ADCs (AFE792x only)
- Maximum RF signal bandwidth:
- TX/FB: 1200 MHz (AFE7920/88) or 400 MHz (AFE7989) or 800MHz (AFE7921)
- RX: 600 MHz (AFE7920/88) or 400 MHz (AFE7921/AFE7989)
- Digital Step
Attenuators (DSA):
- TX: 40 dB range, 1-dB analog and 0.125-dB digital steps
- RX: 25 dB range, 0.5-dB steps
- FB: 25 dB range, 0.5-dB steps
- Single or dual-band DUC/DDCs (AFE7920/88 only) for TX and RX
- Dual NCOs for fast frequency switching
- Supports TDD operation with fast switching between TX and RX
- Internal PLL/VCO to generate DAC/ADC clocks
- Optional external CLK at DAC or ADC rate
- SerDes data interface:
- JESD204B and JESD204C compliant
- 8 SerDes transceivers up to 29.5 Gbps
- 8b/10b and 64b/66b encoding
- 12-bit, 16-bit, 24-bit, and 32-bit resolution
- Subclass 1 multi-device synchronization
- Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
The AFE79xx is a family of high performance, wide bandwidth multi-channel transceivers, integrating four RF sampling transmitter chains, four RF sampling receiver chains, and up to two RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows the device to generate and receive 3G, 4G, and 5G signals from wireless base stations, while the wide bandwidth capability of the AFE79xx devices is designed for multi-band 4G and 5G base stations.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The single or dual digital down converters (DDC) provide up to 600 MHz of combined signal BW. In TDD mode, the receiver channel can be configured to dynamically switch between the traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of re-using the same analog input for both purposes.
Each transmitter chain includes a single or dual digital up converters (DUCs) supporting up to 1200-MHz combined signal bandwidth. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd or 3rd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
The feedback path includes an 25-dB range DSA driving a 3-GSPS RF sampling ADC, followed by a DDC with up to 1200-MHz bandwidth.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | AFE79xx Quad-Channel RF Transceiver With Feedback Path 数据表 (Rev. C) | PDF | HTML | 2020-6-23 | ||
| 应用手册 | RF Sampling Resource Guide. | PDF | HTML | 英语版 | PDF | HTML | 2024-3-6 | |
| 用户指南 | AFE7769DEVM 与 Hitek Agilex eSOM7 FPGA 连接 | PDF | HTML | 英语版 | PDF | HTML | 2023-10-18 | |
| 应用手册 | 从 JESD204B 升级到 JESD204C 时的系统设计注意事项 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | 2021-5-3 | ||
| 应用手册 | AFE79xx 布局指南 (Rev. B) | PDF | HTML | 英语版 (Rev.B) | 2021-5-3 | ||
| 应用手册 | AFE79xx AGC+LNA Bypass参数设置 | 2021-4-1 | ||||
| 应用手册 | AGC简述 | 2020-9-25 | ||||
| 应用手册 | AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing | 2020-4-15 | ||||
| 应用手册 | Temp Profile to Maintain Optimum FIT Performance | 2019-7-23 |
设计与开发
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