ADS4149

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14 位、250MSPS 模数转换器 (ADC)

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数据表

document-pdfAcrobat 12-/14-Bit, 160/250MSPS, Ultralow-Power ADC 数据表 (Rev. G) (英语)

用户指南

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (英语)

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ADS4149

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数据表

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产品详情

Sample rate (max) (Msps)

250

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

265

Architecture

Pipeline

SNR (dB)

72.2

ENOB (Bits)

11.5

SFDR (dB)

88

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

250

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

800

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

265

Architecture

Pipeline

SNR (dB)

72.2

ENOB (Bits)

11.5

SFDR (dB)

88

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
- 201mW Total Power at 160MSPS
- 265mW Total Power at 250MSPS
High Dynamic Performance:
- SNR: 70.6dBFS at 170MHz
- SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To 200mV_PP
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

Maximum Sample Rate: 250MSPS
Ultralow Power with 1.8V Single Supply:
- 201mW Total Power at 160MSPS
- 265mW Total Power at 250MSPS
High Dynamic Performance:
- SNR: 70.6dBFS at 170MHz
- SFDR: 84dBc at 170MHz
Dynamic Power Scaling with Sample Rate
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude Down To 200mV_PP
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x/4x are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C)

The ADS412x/4x are a family of 12-bit/14-bit analog-to-digital converters (ADCs) with sampling rates up to 250MSPS. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.

The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

The ADS412x/4x are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C)

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技术文档

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查看全部 14

顶层文档	类型	标题	日期
*	数据表	12-/14-Bit, 160/250MSPS, Ultralow-Power ADC 数据表 (Rev. G)	2011-1-20
*	用户指南	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)	2012-7-10
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015-5-22
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013-7-19
	应用手册	Band-Pass Filter Design Techniques for High-Speed ADCs	2012-2-27
	应用手册	High-Speed, Analog-to-Digital Converter Basics	2012-1-11
	应用手册	Power Supply Design for the ADS41xx (Rev. A)	2011-12-29
	用户指南	TSW3725 Evaluation Module	2011-10-25
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010-9-10
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009-4-28
	应用手册	CDCE62005 as Clock Solution for High-Speed ADCs	2008-9-4
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008-6-2
	应用手册	QFN Layout Guidelines	2006-7-28

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评估板

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ADS4149EVM 还包括德州仪器 (TI) 的新款 10 路输出低抖动时钟同步器和抖动消除器器件 - CDCE72010，它可用于驱动 ADS4149 的时钟输入。我们为外部 VCXO 和晶体带通滤波器提供了开放式插槽，允许对组合的高性能 ADC 与时钟电路（相当于最终的系统级解决方案）进行快速评估。此外，还为 (...)

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