NTSC/PAL/SECAM 分量 10 位数字视频解码器,支持 Macrovision™ 检测和 3D-YC/5-Line 通讯




Supply voltage (V) 1.8, 3.3 Operating temperature range (C) 0 to 70 open-in-new 查找其它 HDMI, DisplayPort & MIPI IC


HTQFP (PNP) 128 256 mm² 16 x 16 open-in-new 查找其它 HDMI, DisplayPort & MIPI IC


  • Two 11-Bit 60-MSPS Analog-to-Digital (A/D) Converters With Analog Preprocessors (Clamp/AGC)
  • Fixed RGB-to-YUV Color Space Conversion
  • Robust Sync Detection for Weak and Noisy Signals as Well as VCR
  • Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60) and SECAM (B, D, G, K, K1, L) CVBS, S-Video
  • Supports Component Standards 480i, 576i, 480p, and 576p
  • Supports ITU-R BT.601 Pixel Sampling Frequencies
  • Supports 3D Y/C Separation, or 2D 5-Line (5H) Adaptive Comb and Chroma Trap Filter for Both PAL and NTSC Signals
  • Concurrent Temporal, Frame Recursive, Noise Reduction (3DNR)
  • IF Compensation
  • Line-Based Time Base Correction (TBC)
  • Fast Switch 4x Oversampled Input for Digital RGB Overlay Switching Between Any CVBS, S-Video, or Component Video Input
  • SCART 4x Oversampled Fast Switching Between Component RGB Input and CBVS Input
  • Analog Video Output
  • Chrominance Processor
  • Luminance Processor
  • Clock/Timing Processor and Power-Down Control
  • Output Formatter Supports Both ITU-R BT.656 (Embedded Syncs) and ITU-R BT.601 (4:2:2 With Discrete Syncs)
  • I2C Host Port Interface
  • VBI Data Processor
  • "Blue" Screen (Programmable Color) Output
  • Macrovision™ Copy Protection Detection Circuit (Types 1, 2, and 3) on Both Interlaced and Progressive Signals
  • Applications
    • Digital TV
    • LCD TV/Monitors
    • DVD-R
    • PVR
    • PC Video Cards
    • Video Capture/Video Editing
    • Video Conferencing

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The TVP5160 device is a high quality, digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5160 decoder supports the A/D conversion of component YPbPr and RGB (SCART) signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-Video into component YCbCr. Additionally, component progressive signals can be digitized. The chip includes two 11-bit, 60-MSPS, A/D converters (ADCs). Prior to each ADC, each analog channel contains an analog circuit, which clamps the input to a reference voltage and applies a programmable gain and offset. A total of 12 video input terminals can be configured to a combination of YPbPr, RGB, CVBS, and S-Video video inputs.

Progressive component signals are sampled at 2x clock frequency (54 MHz) and are then decimated to the 1x rate. In SCART mode the component inputs and the CVBS inputs are sampled at 54 MHz alternately, then decimated to the 1x rate. Composite or S-Video signals are sampled at 4x the ITU-R BT.601 clock frequency (54 MHz), line-locked for correct pixel alignment, and are then decimated to the 1x rate. CVBS decoding uses advanced 3D Y/C filtering and 2-dimensional complementary 5-line adaptive comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. 3D Y/C color separation may be used on both PAL and NTSC video signals. A chroma trap filter is also available. On CVBS and Y/C inputs, the user can control video characteristics such as hue, contrast, brightness, and saturation via an I2C host port interface. Furthermore, luma peaking with programmable gain is included, as well as a patented color transient improvement (CTI) circuit. Attenuation at higher frequencies or asymmetrical color subcarrier sidebands are compensated using the IF compensation block. Frame adaptive noise reduction may be applied to reduce temporal noise on CVBS, S-Video, or component inputs.

3D noise reduction and 3D Y/C separation may be used at the same time or independently.

The TVP5160 decoder uses Texas Instruments' patented technology for locking to weak, noisy, or unstable signals and can auto-detect between broadcast quality and VCR-style (nonstandard) video sources.

The TVP5160 decoder generates synchronization, blanking, field, active video window, horizontal and vertical syncs, clock, genlock (for downstream video encoder synchronization), host CPU interrupt and programmable logic I/O signals, in addition to digital video outputs.

The TVP5160 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor (VDP) slices and performs error checking on teletext, closed caption, and other VBI data. A built-in FIFO stores up to 11 lines of teletext data, and, with proper host port synchronization, full-screen teletext retrieval is possible. The TVP5160 decoder can pass through the output formatter 2x sampled raw Luma data for host-based VBI processing.

Digital RGB overlay can be synchronously switched with any video input, with all signals being oversampled at 4x the pixel rate.

The TVP5160 detailed functionality includes:

  • Two high-speed, 60-MSPS, 11-bit, A/D channels with programmable clamp and gain control

    The two ADCs can sample CVBS or S-Video at 54 MHz. YPbPr/RGB is multiplexed between the two ADCs which sample at 54 MHz giving a channel sampling frequency of 27 MHz.

  • Supports ITU-R BT.601 pixel sampling frequencies.

    Supports ITU-R BT.601 sampling for both interlaced and progressive signals.

  • RGB-to-YUV color space conversion for SCART signals
  • 3D Y/C separation or 2D 5-line (5H) adaptive comb and chroma trap filter

    3-frame NTSC and PAL color separation

  • Temporal frame recursive noise reduction (3DNR)

    Frame recursive noise reduction can be applied to interlaced CVBS, S-Video, or component inputs for interlaced signals. Noise reduction can be used at the same time as 3D Y/C separation. Noise reduction cannot be applied to progressive video signals.

  • Line-based time base correction (TBC)

    Line-based time correction corrects for horizontal phase errors encountered during video decoding up to ±80 pixels of error. This improves the output video quality from jittery sources such as VCRs. It also reduces line tearing during video trick modes such as fast forward and rewind.

  • IF compensation

    Attenuation at higher frequencies or asymmetrical color subcarrier sidebands are compensated using the IF compensation block

  • Fast switch 4x oversampling for digital RGB overlay signals for switching between any CVBS, S-Video, or component video inputs

    The fast switch overlay signals (FSO, DR, DG, DB) are oversampled at 4x the pixel clock frequency. The phase of these signals is used to mix the selected video input format and a digital RGB input to generate an output video stream. This improves the overlay picture quality when the external FSO and digital RGB signals are generated by an asynchronous source.

  • SCART 4x oversampled fast switching between component RGB input and CBVS input

    The SCART overlay control signal (FSS) is oversampled at 4x the pixel clock frequency. The phase of this signal is used to mix between the CVBS input and the analog RGB inputs. This improves the analog overlay picture quality when the external FSS and analog video signals are generated by an asynchronous source.

  • Analog video output

    \Buffered analog output with automatic PGA

  • Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60), SECAM (B, D, G, K, K1, L), CVBS, and S-Video
  • Twelve analog video input terminals for multi-source connection
  • User-programmable video output formats 10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs 20-bit 4:2:2 YCbCr with discrete syncs 10-bit 4:2:2 YCbCr with discrete syncs 2x sampled raw VBI data in active video during a vertical blanking period Sliced VBI data during a horizontal blanking period
  • HS/VS outputs with programmable position, polarity, and width and FID (Field ID) output
  • Composite and S-Video processing Adaptive 3D/2D Y/C separation using 5-line adaptive comb filter for composite video inputs; chroma-trap available Automatic video standard detection and switching (NTSC/PAL/SECAM/progressive) Luma-peaking with programmable gain Output data rates either 1x or 2x pixel rate Patented architecture for locking to weak, noisy, or unstable signals Single 14.31818-MHz reference crystal for all standards (ITU-R.BT601 sampling, interlaced or progressive) Line-locked internal pixel sampling clock generation with horizontal and vertical lock signal outputs Certified Macrovision copy protection detection on composite and S-Video inputs (NTSC, PAL) Genlock output (RTC) for downstream video encoder synchronization
  • Vertical blank interval data processor Teletext (NABTS, WST) Closed caption (CC) and extended data service (XDS) Wide screen signaling (WSS) Copy generation management system (CGMS) Video program system (VPS/PDC) Vertical interval time code (VITC) EPG video guide 1x/2x (Gemstar) V-Chip decoding Custom mode Register readback of CC, CGMS, WSS, VPS, VITC, V-Chip, EPG 1x and 2x sliced data, CGMS-A and RC for progressive signals.
  • I2C host port interface
  • "e;Blue"e; screen output
  • Macrovision copy protection detection circuit (types 1, 2, and 3) on both interlaced and progressive signals

    Macrovision detection on standard definition signals of types 1, 2, and 3, and to Revision 1.2 for progressive signals

  • Reduced power consumption: 1.8-V digital core, 3.3-V and 1.8-V analog core with power-save and power-down modes
  • 128-TQFP PowerPAD™ package

    The TVP5160 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP5160 decoder is through a standard I2C host port interface, as described earlier.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.


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类型 标题 下载最新的英文版本 发布
* 数据表 TVP5160 NTSC/PAL/SECAM/Component 2x10-bit Digital Video Decoder 数据表 2011年 4月 19日
技术文章 Small doesn’t mean you compromise performance when implementing signal isolation 2017年 5月 25日
技术文章 Upgrading the standard: a better way to drive peripherals 2014年 6月 20日
技术文章 How Thunderbolt™ 2 enables 4k video resolution 2014年 4月 3日
技术文章 Going for distance or going for speed on the RS-485 bus? 2014年 3月 5日
应用手册 TVP5160 3D Noise Reduction Calibration Procedure 2011年 5月 19日
应用手册 TVP5160 IF Compensation Calibration Procedure 2011年 5月 19日
应用手册 TVP5160 3DYC Operation 2011年 4月 29日
应用手册 TVP5160 Patch Code Download Guidelines 2010年 12月 14日
应用手册 TVP5160 VBI Quick Start 2010年 7月 7日
应用手册 TVP5160 Anti-Aliasing Filters 2010年 6月 25日
应用手册 TVP5160 PCB Layout Guidelines 2010年 6月 16日
用户指南 TVP5160 EVM Quick Start Guide 2005年 4月 18日
用户指南 TVP5160EVM Users Guide 2005年 4月 18日




支持软件 下载
SLEC004.ZIP (5968 KB)


仿真工具 下载
document-generic 用户指南 document-generic 下载英文版本 (Rev.A)


封装 引脚 下载
HTQFP (PNP) 128 视图选项



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