封装信息
| 封装 | 引脚 VSSOP (DGK) | 8 |
| 工作温度范围 (°C) -40 to 125 |
| 包装数量 | 包装 80 | TUBE |
TPS771 的特性
- Open Drain Power-On Reset With 220-ms Delay (TPS771xx)
- Open Drain Power-Good (PG) Status Output (TPS772xx)
- 150-mA Low-Dropout Voltage Regulator
- Available in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
- Dropout Voltage Typically 115 mV
at 150 mA (TPS77133, TPS77233) - Ultralow 92-uA Quiescent Current (Typ)
- 8-Pin MSOP (DGK) Package
- Low Noise (55 uVrms) Without External Filter (Bypass) Capacitor (TPS77118, TPS77218)
- 2% Tolerance Over Specified Conditions
for Fixed-Output Versions - Fast Transient Response
- Thermal Shutdown Protection
TPS771 的说明
The TPS771xx and TPS772xx are low-dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 150 mA of output current with a dropout of 115 mV (TPS77133, TPS77233). Quiescent current is 92 uA at full load dropping down to 1 uA when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10uF) or low capacitance (1uF) tantalum capacitors. These devices have extremely low noise output performance (55 uVrms) without using any added filter capacitors. TPS771xx and TPS772xx are designed to have fast transient response for larger load current changes.
The TPS771xx or TPS772xx is offered in 1.5 V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK) packages.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 uA over the full range of output current, 0 mA to 150 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN\ pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN\ (enable) shuts down the regulator, reducing the quiescent current to less than 1 uA at TJ = 25°C.
The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS) or reset output voltage. The RESET\ output of the TPS771xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET\ will go to a high-impedance state after a 220 ms delay. RESET\ will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage.
For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage.