THS8200

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三通道 10 位全格式视频 DAC

产品详情

Rating Catalog Operating temperature range (°C) 0 to 70
Rating Catalog Operating temperature range (°C) 0 to 70
HTQFP (PFP) 80 196 mm² 14 x 14
  • Overall
    • Three 11-Bit 205-MSPS Digital-to-Analog Converters (DACs) With Integrated Bi-Level or Tri-Level Sync Insertion
    • Support for All ATSC Video Formats (Including 1080P) and PC Graphics Formats (up to UXGA at 75 Hz)
  • Input
    • Flexible 10-, 15-, 16-, 20-, 24-, or 30-Bit Digital Video Input Interface With Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 Sampled
    • Video Synchronization by Hsync or Vsync Dedicated Inputs or by Extraction of Embedded SAV and EAV Codes According to ITU-R.BT601 (SDTV) or SMPTE 274M and SMPTE 296M (HDTV)
    • Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can Receive Video-Over-DVI Formats According to the EIA-861 Specification and Convert to YPbPr or RGB Component Formats With Separate Syncs or Embedded Composite Sync.
  • Video Processing
    • Programmable Clip/Shift/Multiply Function for Operation With Full-Range or ITU-R.BT601 Video Range Input Data
    • Programmable Digital Fine-Gain Controller on Each Analog Output Channel, for Accurate Channel Matching and Programmable White-Balance Control
    • Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
    • Built-In 2x Oversampling SDTV and HDTV Interpolation Filter for Improved Video Frequency Characteristic
    • Fully Programmable Digital Color Space Conversion Circuit
    • Fully Programmable Display Timing Generator to Supply All SDTV and HDTV Composite Sync Timing Formats, Progressive and Interlaced
    • Fully Programmable Hsync and Vsync Outputs
    • Vertical Blanking Interval (VBI) Override or Data Pass-Through for VBI Data Transparency
    • Programmable CGMS Data Generation and Insertion
  • Output
    • Digital
      • ITU-R BT.656 Digital Video Output Port
    • Analog
      • Analog Component Output from Software-Switchable 700-mV or 1.3-V Compliant Output DACs at 37.5-Ω Load
      • Programmable Video/Sync Ratio (7:3 or 10:4)
      • Programmable Video Pedestal
  • General
    • Built-In Video Color Bar Test Pattern Generator
    • Fast Mode I2C Control Interface
    • Configurable Master or Slave Timing Mode
      • Configuration Modes Allow the Device to Act as a Master Timing Source for Requesting Data From, for Example, the Video Frame Buffer (Master Mode Only Available for PC Graphics Output Modes).
      • Alternatively, the Device Can Slave to an External Timing Master.
    • DAC and Chip Power-Down Modes
    • Low-Power 1.8-V and 3.3-V Operation
    • 80-Pin PowerPAD Plastic Quad Flatpack Package With Efficient Heat Dissipation and Small Physical Size
  • Overall
    • Three 11-Bit 205-MSPS Digital-to-Analog Converters (DACs) With Integrated Bi-Level or Tri-Level Sync Insertion
    • Support for All ATSC Video Formats (Including 1080P) and PC Graphics Formats (up to UXGA at 75 Hz)
  • Input
    • Flexible 10-, 15-, 16-, 20-, 24-, or 30-Bit Digital Video Input Interface With Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 Sampled
    • Video Synchronization by Hsync or Vsync Dedicated Inputs or by Extraction of Embedded SAV and EAV Codes According to ITU-R.BT601 (SDTV) or SMPTE 274M and SMPTE 296M (HDTV)
    • Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can Receive Video-Over-DVI Formats According to the EIA-861 Specification and Convert to YPbPr or RGB Component Formats With Separate Syncs or Embedded Composite Sync.
  • Video Processing
    • Programmable Clip/Shift/Multiply Function for Operation With Full-Range or ITU-R.BT601 Video Range Input Data
    • Programmable Digital Fine-Gain Controller on Each Analog Output Channel, for Accurate Channel Matching and Programmable White-Balance Control
    • Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
    • Built-In 2x Oversampling SDTV and HDTV Interpolation Filter for Improved Video Frequency Characteristic
    • Fully Programmable Digital Color Space Conversion Circuit
    • Fully Programmable Display Timing Generator to Supply All SDTV and HDTV Composite Sync Timing Formats, Progressive and Interlaced
    • Fully Programmable Hsync and Vsync Outputs
    • Vertical Blanking Interval (VBI) Override or Data Pass-Through for VBI Data Transparency
    • Programmable CGMS Data Generation and Insertion
  • Output
    • Digital
      • ITU-R BT.656 Digital Video Output Port
    • Analog
      • Analog Component Output from Software-Switchable 700-mV or 1.3-V Compliant Output DACs at 37.5-Ω Load
      • Programmable Video/Sync Ratio (7:3 or 10:4)
      • Programmable Video Pedestal
  • General
    • Built-In Video Color Bar Test Pattern Generator
    • Fast Mode I2C Control Interface
    • Configurable Master or Slave Timing Mode
      • Configuration Modes Allow the Device to Act as a Master Timing Source for Requesting Data From, for Example, the Video Frame Buffer (Master Mode Only Available for PC Graphics Output Modes).
      • Alternatively, the Device Can Slave to an External Timing Master.
    • DAC and Chip Power-Down Modes
    • Low-Power 1.8-V and 3.3-V Operation
    • 80-Pin PowerPAD Plastic Quad Flatpack Package With Efficient Heat Dissipation and Small Physical Size

The THS8200 device is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.

The THS8200 device can accept a variety of digital input formats, in 4:4:4 and 4:2:2 formats, over an interface of three, two, or one 10‑bit ports. The device synchronizes to incoming video data either through dedicated Hsync and Vsync inputs or through extraction of the sync information from embedded sync (SAV and EAV) codes inside the video stream. Alternatively, when the THS8200 is configured for generating PC graphics output, the device also provides a master timing mode in which it requests video data from an external (memory) source.

The THS8200 device contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully programmable 3x3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2x oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.

The output compliance range can be set through external adjustment resistors, and there is a choice of two settings to accommodate both component video or PC graphics (700-mV) and composite video (1.3‑V) outputs without hardware changes. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. To avoid nonlinearities after scaling of the video range, the DACs have 11-bit resolution internally. Furthermore, a bi-level or tri-level sync with programmable amplitude (to support both 700-mV:300-mV and 714-mV:286-mV video:sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range and preserves 100% of the 11-bit dynamic range of the DAC for video data.

The THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.

The THS8200 device is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.

The THS8200 device can accept a variety of digital input formats, in 4:4:4 and 4:2:2 formats, over an interface of three, two, or one 10‑bit ports. The device synchronizes to incoming video data either through dedicated Hsync and Vsync inputs or through extraction of the sync information from embedded sync (SAV and EAV) codes inside the video stream. Alternatively, when the THS8200 is configured for generating PC graphics output, the device also provides a master timing mode in which it requests video data from an external (memory) source.

The THS8200 device contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully programmable 3x3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2x oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.

The output compliance range can be set through external adjustment resistors, and there is a choice of two settings to accommodate both component video or PC graphics (700-mV) and composite video (1.3‑V) outputs without hardware changes. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. To avoid nonlinearities after scaling of the video range, the DACs have 11-bit resolution internally. Furthermore, a bi-level or tri-level sync with programmable amplitude (to support both 700-mV:300-mV and 714-mV:286-mV video:sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range and preserves 100% of the 11-bit dynamic range of the DAC for video data.

The THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

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类型 标题 下载最新的英语版本 日期
* 数据表 THS8200 All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion 数据表 (Rev. E) PDF | HTML 2014年 9月 18日
应用手册 THS8200 PCB Layout Guidelines 2010年 6月 16日
应用手册 Noise Analysis for High Speed Op Amps (Rev. A) 2005年 1月 17日
应用手册 使用 DM642 DSP 和 THS8200 驱动器的高分辨率视频 (Rev. A) 2004年 5月 3日
应用手册 Analog Reconstruction Filter for HDTV Using THS8133, THS8134, THS8135, THS8200 2001年 9月 14日

设计和开发

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软件编程工具

SLEC026 THS8200 Setup Files

支持的产品和硬件

支持的产品和硬件

产品
HDMI、DisplayPort 和 MIPI IC
THS8200 三通道 10 位全格式视频 DAC
支持软件

SLEC029 TVP7002 + THS8200 EVM Kit Setup

支持的产品和硬件

支持的产品和硬件

产品
HDMI、DisplayPort 和 MIPI IC
THS8200 三通道 10 位全格式视频 DAC TVP7002 三路 8/10 位 165/110MSPS 视频 ADC TVP70025I 具有水平 PLL 的三路 10 位 90MSPS 视频和图形数字转换器
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