SN74CB3Q3244
- High-bandwidth data path (up to 500MHz)
- 5V-tolerant I/Os with device powered-up or powered-down
- Low and flat ON-state resistance (ron) characteristics over operating range
- Rail-to-rail switching on data I/O ports
- 0 to 5V switching with 3.3V VCC
- 0 to 3.3V switching with 2.5V VCC
- Bidirectional data flow, with near-zero propagation delay
- Low input and output capacitance minimizes loading and signal distortion
- Fast switching frequency
- Data and control inputs provide undershoot clamp diodes
- Low power consumption
- VCC operating range from 2.3V to 3.6V
- Data I/Os support 0 to 5V signaling levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
- Control inputs can be driven by TTL or 5V/3.3V CMOS outputs
- Ioff supports partial-power-down mode operation
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD performance tested per JESD 22
- 2000V human-body model (A114B, Class II)
- 1000V charged-device model (C101)
- Supports both digital and analog applications: differential signal interface, memory interleaving, bus isolation, low-distortion signal gating
The SN74CB3Q3244 is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3244 provides an optimized interface design for broadband communications, networking, and data-intensive computing systems.
The SN74CB3Q3244 is organized as two 4-bit bus switches with separate output-enable (1 OE, 2 OE) inputs. The device can be used as two 4-bit bus switches or as one 8-bit bus switch. When OE is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 4-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when powered down. The device has isolation during power off.
To make sure of the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| 应用手册 | 选择正确的德州仪器 (TI) 信号开关 (Rev. E) | PDF | HTML | 英语版 (Rev.E) | PDF | HTML | 2022-8-5 | |
| 应用手册 | 多路复用器和信号开关词汇表 (Rev. B) | 英语版 (Rev.B) | PDF | HTML | 2022-3-11 | ||
| 应用简报 | 利用关断保护信号开关消除电源时序 (Rev. C) | 英语版 (Rev.C) | PDF | HTML | 2021-10-21 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
LEADED-ADAPTER1 — 表面贴装转 DIP 接头适配器，用于快速测试 TI 的 5、8、10、16 和 24 引脚引线式封装。
EVM-LEADED1 电路板可用于对 TI 的常见引线式封装进行快速测试和电路板试验。 该电路板具有足够的空间，可将 TI 的 D、DBQ、DCT、DCU、DDF、DGS、DGV 和 PW 表面贴装封装转换为 100mil DIP 接头。
PMP23630 — 适用于 HVDC 30kW PSU 的数据中心参考设计
此参考设计是一款两级高效 30kW 电源，具有高压直流 (HVDC) 输出。第一级是由三相输入源供电的三级飞跨电容器功率因数校正 (PFC) 转换器。PFC 控制由 TMS320F28P650DK 高性能微控制器实现。由于电感器中的频率加倍效应，因此选择飞跨电容器拓扑而不是更传统的拓扑（例如 Vienna 整流器）。这种情况下，电感器的尺寸越来越小，效率也越来越高。PFC 之后连接着两个 Δ-Δ 连接的三相电感器-电感器-电容器 (LLC) 转换器。一个 LLC 用于 +400V，一个用于 -400V。LLC 转换器可以配置为单独的电源或单个 800V 输出。Δ-Δ 连接可提供更低的均方根 (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SSOP (DBQ) | 20 | Ultra Librarian |
| TVSOP (DGV) | 20 | Ultra Librarian |
| TSSOP (PW) | 20 | Ultra Librarian |
| VQFN (RGY) | 20 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。