DS92LV18

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18 位总线 LVDS 串行器/解串器 - 15-66MHz

产品详情

Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2376 Input signal BLVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2376 Input signal BLVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PN) 80 196 mm² 14 x 14
  • 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
  • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
  • ±100 mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.0kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

  • 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
  • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
  • ±100 mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.0kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

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类型 标题 下载最新的英语版本 日期
* 数据表 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz 数据表 (Rev. E) 2013年 4月 18日
应用手册 DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013年 4月 29日
应用手册 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) 2013年 4月 26日
用户指南 18-Bit SerDes Evaluation Kit User Manual 2012年 1月 25日
应用手册 App Note 1909 DS15BA101 & DS15EA101 Enable Long Reach Apps for Embed Clk SERDES 2009年 3月 2日
设计指南 18-bit SerDes Design Guide (DS92LV18, SCAN921821) 2007年 3月 29日

设计和开发

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评估板

LVDS-18B-EVK — 18 位总线 LVDS SERDES 评估板 15-66 MHz

The LVDS-18B-EVK is a complete kit for evaluation of National Semiconductor's 18-bit SerDes devices (DS92LV18 and SCAN921821) with low cost twisted pair cables as well as other 100-ohm differential cables.

用户指南: PDF
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用户指南: PDF
英语版 (Rev.A): PDF
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LQFP (PN) 80 Ultra Librarian

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