DS92LV16
- 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
- Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
- Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
- Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
- Line and Local Loopback Modes
- Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
- No External Coding Required
- Internal PLL, No External PLL Components Required
- Single +3.3V Power Supply
- Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
- ±100mV Receiver Input Threshold
- Loss of Lock Detection and Reporting Pin
- Industrial −40 to +85°C Temperature Range
- >2.5kV HBM ESD
- Compact, Standard 80-Pin LQFP Package
All trademarks are the property of their respective owners.
The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.
The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz 数据表 (Rev. H) | 2013-4-16 | |||
| 应用手册 | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013-4-29 | ||||
| 应用手册 | DS92LV16 Power Up Reset (Rev. B) | 2013-4-26 | ||||
| 应用手册 | How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) | 2013-4-26 | ||||
| 应用手册 | External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) | 2013-4-26 | ||||
| 应用手册 | App Note 1909 DS15BA101 & DS15EA101 Enable Long Reach Apps for Embed Clk SERDES | 2009-3-2 | ||||
| 设计指南 | DS92LV16 16-bit SerDes Design Guide | 2007-3-29 | ||||
| 白皮书 | Easy-to-Use LVDS Serdes for the Serdes Neophyte | 2001-9-1 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| LQFP (PN) | 80 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。