DS90UR124 5-43MHz DC 平衡 24 位 FPD 链接 II 解串器 | 德州仪器 TI.com.cn

DS90UR124
此产品已上市,且可供购买。 可提供某些产品的较新替代品。
5-43MHz DC 平衡 24 位 FPD 链接 II 解串器

 

备选器件推荐

  • DS90C124  -  Deserializer, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
  • DS90C124-Q1  -  Deserializer, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
  • DS90UR124-Q1  - 器件与被比较器件具有相似功能,但并不功能等效。 
  • DS90C241  -  Serializer, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
  • DS90C241-Q1  -  Serializer, 5-35 MHz, –40°C To +105°C, 10 Meter Drive Strength
  • DS90UR241  -  Deserializer, 5-43 MHz, –40°C To +105°C, 10 Meter Drive Strength (FOR COMPLETE CHIPSET)
  • DS90UR241-Q1  -  Deserializer, 5-43 MHz, –40°C To +105°C, 10 Meter Drive Strength (FOR COMPLETE CHIPSET)
  • DS99R101  -  Serializer & DS99R102 Deserializer Chipset, 3-40 MHz, 0°C To +70°C, 2 Meter Drive Strength
  • DS99R103  -  Serializer & DS99R104 Deserializer Chipset, 3-40 MHz, -40°C To +85°C, 5 Meter Drive Strength
  • DS99R105  -  Serializer & DS99R106 Deserializer Chipset, 3-40 MHz, 0°C To +70°C, 10 Meter Drive Strength

描述

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

特性

  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2
    Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports
    AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM
    ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread
    Spectrum Input; Data Randomization and
    Shuffling on Serial Link; Deserializer Provides
    Adjustable PTO (Progressive Turnon) LVCMOS
    Outputs
  • @Speed BIST (Built-In Self-Test) to Validate
    LVDS Transmission Path
  • Individual Power-Down Controls for Both
    Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin
    TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With
    DS90C241/DS90C124

参数

与其它产品相比 显示 SerDes 邮件 下载到电子表格中
Part number 立即下单 Function Color depth (bpp) Pixel clock min (MHz) Pixel clock (Max) (MHz) Input compatibility Output compatibility Features Signal conditioning EMI reduction Diagnostics Total throughput (Mbps) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG)
DS90UR124 立即下单 Deserializer     18     5     43     FPD-Link II LVDS     LVCMOS     Capable to Drive up to 10 meters STP Cable
Hot Plug Support    
VOD Select
Pre-Emphasis
DC Balance    
Adjustable Progressive Turn On (PTO)
Slew Rate Control    
BIST     1032     Catalog     -40 to 105     TQFP | 64     64TQFP: 144 mm2: 12 x 12 (TQFP | 64)    
DS90C124 无样片 Deserializer     18     5     35     FPD-Link II LVDS     LVCMOS     LOCK Output
All Codes RDL to Support Live-Pluggable Applications
Embedded Clock CDR
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver    
Pre-Emphasis
VOD Select
DC Balance    
Progressive Turn On (PTO)
Slew Rate Control    
BIST     840     Catalog     -40 to 105     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)    
DS90C124-Q1 立即下单 Deserializer     18     5     35     FPD-Link II LVDS     LVCMOS     LOCK Output
All Codes RDL to Support Live-Pluggable Applications
Embedded Clock CDR
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver    
Pre-Emphasis
VOD Select
DC Balance    
Progressive Turn On (PTO)
Slew Rate Control    
BIST     840     Automotive     -40 to 105     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)    
DS90C241 立即下单 Serializer     18     5     35     LVCMOS     FPD-Link LVDS     LOCK Output
All Codes RDL to Support Live-Pluggable Applications
Embedded Clock CDR
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver    
Pre-Emphasis
VOD Select    
Progressive Turn On (PTO)
LVDS    
    840     Catalog     -40 to 105     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)    
DS90C241-Q1 立即下单 Serializer     18     5     35     LVCMOS     FPD-Link LVDS     LOCK Output
All Codes RDL to Support Live-Pluggable Applications
Embedded Clock CDR
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver    
Pre-Emphasis
VOD Select    
Progressive Turn On
LVDS    
    840     Automotive     -40 to 105     TQFP | 48     48TQFP: 81 mm2: 9 x 9 (TQFP | 48)    
DS90UR124-Q1 立即下单 Deserializer     18     5     43     FPD-Link II LVDS     LVCMOS     Capable to Drive up to 10 meters STP Cable
Hot Plug Support    
VOD Select
Pre-Emphasis
DC Balance