CDCVF2505-Q1 不推荐用于新设计
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CDCVF2505 正在供货 用于同步 DRAM和通用应用且具有展频功能、断电模式的 PLL 时钟驱动器 Can achieve better performance

产品详情

Function Memory interface Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 150 Operating temperature range (°C) -40 to 85 Rating Automotive
Function Memory interface Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 150 Operating temperature range (°C) -40 to 85 Rating Automotive
SOIC (D) 8 29.4 mm² 4.9 x 6
  • Qualified for Automotive Applications
  • Phase-Locked Loop Clock Driver for Synchronous DRAM
    and General-Purpose Applications
  • Spread-Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): <150 ps Over the
    Range 66 MHz to 200 MHz
  • Distributes One Clock Input to One Bank of Five Outputs
    (CLKOUT Is Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin SOIC Package
  • Consumes Less Than 100 µA (Typically) in
    Power Down Mode
  • Internal Feedback Loop Is Used to Synchronize the
    Outputs to the Input Clock
  • 25- On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the
    Need for External Components

  • Qualified for Automotive Applications
  • Phase-Locked Loop Clock Driver for Synchronous DRAM
    and General-Purpose Applications
  • Spread-Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-to-Cycle): <150 ps Over the
    Range 66 MHz to 200 MHz
  • Distributes One Clock Input to One Bank of Five Outputs
    (CLKOUT Is Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is No Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin SOIC Package
  • Consumes Less Than 100 µA (Typically) in
    Power Down Mode
  • Internal Feedback Loop Is Used to Synchronize the
    Outputs to the Input Clock
  • 25- On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the
    Need for External Components

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.

The CDCVF2505 is characterized for operation from –40°C to 85°C.

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类型 标题 下载最新的英语版本 日期
* 数据表 3.3-V Clock Phase-Locked Loop Clock Driver 数据表 2008年 11月 21日

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点