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运算放大器 (op amps)
高速运算放大器 (GBW ≥ 50MHz)

BUF602

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1000MHz 高带宽高速闭环缓冲器

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数据表

BUF602

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数据表 立即订购

产品详情

Architecture Closed Loop/Buffer Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.8 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 12.6 GBW (typ) (MHz) 1000 BW at Acl (MHz) 1000 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 8000 Vn at flatband (typ) (nV√Hz) 4.8 Vn at 1 kHz (typ) (nV√Hz) 5.9 Iq per channel (typ) (mA) 5.8 Vos (offset voltage at 25°C) (max) (mV) 30 Rail-to-rail No Rating Catalog Operating temperature range (°C) -45 to 85 Input bias current (max) (pA) 7000000 Offset drift (typ) (µV/°C) 125 Iout (typ) (mA) 60 2nd harmonic (dBc) 76 3rd harmonic (dBc) 98 Frequency of harmonic distortion measurement (MHz) 5
Architecture Closed Loop/Buffer Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.8 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 12.6 GBW (typ) (MHz) 1000 BW at Acl (MHz) 1000 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 8000 Vn at flatband (typ) (nV√Hz) 4.8 Vn at 1 kHz (typ) (nV√Hz) 5.9 Iq per channel (typ) (mA) 5.8 Vos (offset voltage at 25°C) (max) (mV) 30 Rail-to-rail No Rating Catalog Operating temperature range (°C) -45 to 85 Input bias current (max) (pA) 7000000 Offset drift (typ) (µV/°C) 125 Iout (typ) (mA) 60 2nd harmonic (dBc) 76 3rd harmonic (dBc) 98 Frequency of harmonic distortion measurement (MHz) 5
SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • Wide Bandwidth: 1000MHz
  • High Slew Rate: 8000V/µs
  • Flexible Supply Range:
    ±1.4V to ±6.3V Dual Supplies
    +2.8V to +12.6V Single Supply
  • Output Current: 60mA (continuous)
  • Peak Output Current: 350mA
  • Low Quiescent Current: 5.8mA
  • Standard Buffer Pinout
  • Optional Mid-Supply Reference Buffer
  • APPLICATIONS
    • Low Impedance Reference Buffers
    • Clock Distribution Circuits
    • Video/Broadcast Equipment
    • Communications Equipment
    • High-Speed Data Acquisition
    • Test Equipment and Instrumentation

All other trademarks are the property of their respective owners.
  • Wide Bandwidth: 1000MHz
  • High Slew Rate: 8000V/µs
  • Flexible Supply Range:
    ±1.4V to ±6.3V Dual Supplies
    +2.8V to +12.6V Single Supply
  • Output Current: 60mA (continuous)
  • Peak Output Current: 350mA
  • Low Quiescent Current: 5.8mA
  • Standard Buffer Pinout
  • Optional Mid-Supply Reference Buffer
  • APPLICATIONS
    • Low Impedance Reference Buffers
    • Clock Distribution Circuits
    • Video/Broadcast Equipment
    • Communications Equipment
    • High-Speed Data Acquisition
    • Test Equipment and Instrumentation

All other trademarks are the property of their respective owners.

The BUF602 is a closed-loop buffer recommended for a wide range of applications. Its wide bandwidth (1000MHz) and high slew rate (8000V/µs) make it ideal for buffering very high-frequency signals. For AC-coupled applications, an optional mid-point reference (VREF) is provided, reducing the number of external components required and the necessary supply current to provide that reference.

The BUF602 is available in a standard SO-8 surface-mount package and in an SOT23-5 where a smaller footprint is needed.

The BUF602 is a closed-loop buffer recommended for a wide range of applications. Its wide bandwidth (1000MHz) and high slew rate (8000V/µs) make it ideal for buffering very high-frequency signals. For AC-coupled applications, an optional mid-point reference (VREF) is provided, reducing the number of external components required and the necessary supply current to provide that reference.

The BUF602 is available in a standard SO-8 surface-mount package and in an SOT23-5 where a smaller footprint is needed.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 High-Speed, Closed-Loop Buffer 数据表 (Rev. B) 2008-5-22
电子书 The Signal e-book: 有关运算放大器设计主题的博客文章汇编 PDF | HTML 英语版 PDF | HTML 2018-1-31
用户指南 DEM-BUF-SO-1A Demonstration Fixture (Rev. B) 2012-4-12
用户指南 DEM-BUF-SOT-1A User's Guide (Rev. A) 2011-4-22

设计与开发

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评估板

DEM-BUF-SO-1A — DEM-BUF-SO-1A

DEM-BUF-SO-1A 是一个帮助设计人员评估 TI 高速、闭环缓冲器操作和性能的演示装置。此未装件的 PC 板与采用 8 引线 SOIC (D) 封装的产品兼容。

有关此类缓冲放大器以及实用 PCB 布局设计要点的更多信息，请参阅 BUF602 数据表。

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评估板

DEM-BUF-SOT-1A — DEM-BUF-SOT-1A

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仿真模型

BUF602 PSpice Model (Rev. B)

SBOJ002B.ZIP (39 KB) - PSpice 模型
支持的产品和硬件
仿真模型

BUF602 TINA-TI Reference Design

SBOMA37.TSC (2972 KB) - TINA-TI 参考设计
支持的产品和硬件
仿真模型

BUF602 TINA-TI Spice Model

SBOMA38.ZIP (6 KB) - TINA-TI Spice 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
SOT-23 (DBV) 5 Ultra Librarian
SOIC (D) 8 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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