驱动程序或库
AFE79XX-WI-DESIGN — AFE79xx Design Resources for Wireless infrastructure
AFE79xx Design Resources for Wireless infrastructure
AFE7989
- Quad RF sampling 12-GSPS transmit DACs
- Quad RF sampling 3-GSPS receive ADCs
- Dual RF sampling 3-GSPS feedback ADCs (AFE792x only)
- Maximum RF signal bandwidth:
- TX/FB: 1200 MHz (AFE7920/88) or 400 MHz (AFE7989) or 800MHz (AFE7921)
- RX: 600 MHz (AFE7920/88) or 400 MHz (AFE7921/AFE7989)
- Digital Step Attenuators (DSA):
- TX: 40 dB range, 1-dB analog and 0.125-dB digital steps
- RX: 25 dB range, 0.5-dB steps
- FB: 25 dB range, 0.5-dB steps
- Single or dual-band DUC/DDCs (AFE7920/88 only) for TX and RX
- Dual NCOs for fast frequency switching
- Supports TDD operation with fast switching between TX and RX
- Internal PLL/VCO to generate DAC/ADC clocks
- Optional external CLK at DAC or ADC rate
- SerDes data interface:
- JESD204B and JESD204C compliant
- 8 SerDes transceivers up to 29.5 Gbps
- 8b/10b and 64b/66b encoding
- 12-bit, 16-bit, 24-bit, and 32-bit resolution
- Subclass 1 multi-device synchronization
- Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
The AFE79xx is a family of high performance, wide bandwidth multi-channel transceivers, integrating four RF sampling transmitter chains, four RF sampling receiver chains, and up to two RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows the device to generate and receive 3G, 4G, and 5G signals from wireless base stations, while the wide bandwidth capability of the AFE79xx devices is designed for multi-band 4G and 5G base stations.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The single or dual digital down converters (DDC) provide up to 600 MHz of combined signal BW. In TDD mode, the receiver channel can be configured to dynamically switch between the traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of re-using the same analog input for both purposes.
Each transmitter chain includes a single or dual digital up converters (DUCs) supporting up to 1200-MHz combined signal bandwidth. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd or 3rd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
The feedback path includes an 25-dB range DSA driving a 3-GSPS RF sampling ADC, followed by a DDC with up to 1200-MHz bandwidth.
技术文档
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查看全部 7 | 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | AFE79xx Quad-Channel RF Transceiver With Feedback Path 数据表 (Rev. C) | PDF | HTML | 2020年 6月 23日 | ||
| 用户指南 | AFE7769DEVM 与 Hitek Agilex eSOM7 FPGA 连接 | PDF | HTML | 英语版 | PDF | HTML | 2023年 10月 18日 | |
| 应用手册 | AFE79xx 布局指南 (Rev. B) | PDF | HTML | 英语版 (Rev.B) | 2021年 5月 3日 | ||
| 应用手册 | 从 JESD204B 升级到 JESD204C 时的系统设计注意事项 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | 2021年 5月 3日 | ||
| 应用手册 | AGC简述 | 2020年 9月 25日 | ||||
| 应用手册 | AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing | 2020年 4月 15日 | ||||
| 应用手册 | Temp Profile to Maintain Optimum FIT Performance | 2019年 7月 23日 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
评估板
AFE7920EVM — AFE7920 四发射四接收、双反馈路径射频采样收发器评估模块
AFE7920 评估模块 (EVM) 是一个射频采样收发器平台，通过配置可同时支持最多四个发射、四个接收和两个反馈 (4T4R+2FB) 通道。
此电路板可评估 AFE7920 器件，这是一款四通道射频采样模拟前端 (AFE)，具有 14 位 12GSPS 数模转换器 (DAC)、14 位 3GSPS 模数转换器 (ADC) 以及为 DAC 和 ADC 生成高频时钟的片上集成锁相环 (PLL) 和压控振荡器 (VCO)。
AFE7920EVM 可在每个通道使用双频带数字升压转换器和降压转换器，从而同时将具有高动态范围的多个宽带信号合成并实现数字化。接收通道支持片上集成数字步进衰减器 (...)
评估板
HTK-3P-AGILEX-ESOM7 — HITEK Agilex eSOM7 with FMC+ connector to RF transceiver EVMs
The Hitek Systems eSOM7 interfaces with the AFE8092, AFE8030, AFE7952, and AFE7920 through an FPGA mezzanine card (FMC) connector. It provides a quick evaluation and prototyping platform for 5G wireless solutions based on Intel’s latest high-performance 10-nm Agilex F-Series FPGA.
固件
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
支持的产品和硬件
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
订购和质量
包含信息：
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
包含信息：
- 制造厂地点
- 封装厂地点