Flyback Aux Winding OVP and UVLO Fault Sensing Design and Troubleshooting Tips
- SLUAAC5 August 2021 UCC28700 , UCC28701 , UCC28702 , UCC28703 , UCC28704 , UCC28710 , UCC28711 , UCC28712 , UCC28713 , UCC28720 , UCC28722 , UCC28730 , UCC28740 , UCC28742 , UCC28910 , UCC28911

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APPLICATION NOTE

Flyback Aux Winding OVP and UVLO Fault Sensing Design and Troubleshooting Tips

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1 Introduction

Texas Instruments has developed discontinuous mode (DCM) flyback controllers that use transformer coupling to sense the input voltage (V_IN) and output voltage (V_OUT) for power supply control; as well as, circuit fault protection. These voltages are sensed across the flyback transformer (T1) auxiliary winding (V_AUX) of the flyback converter shown in Figure 1-1. The problem with this technique is if the aux winding is noisy it could falsely trigger and input under voltage lockout (UVLO) fault or an output over voltage protection (OVP) fault and unexpectedly shut down the system. The purpose of this application report is to give design guidance to resolve and avoid false OVP and UVLO faults caused by noise on the aux winding. TI primary-side regulated (PSR) DCM flyback controllers that use this kind of auxiliary winding sensing for OVP and UVLO are the UCC28700/1/2/3/4, UCC28710/1/2/3, UCC28720/22 UCC28730, UCC28910/1. The UCC28740/2 secondary side regulated (SSR) controllers also use auxiliary winding fault sensing.

Figure 1-1 DCM Flyback Converter Using Auxiliary Winding Sensing to Detect Input UVLO and OVP

2 Brief Review of DCM FM, AM, FM Flyback Control Law

The DCM flyback controllers presented here use Frequency Modulation (FM) and Primary Peak Current Modulation (AM) to control the flyback converters frequency, duty cycle, primary peak current and output voltage. These controllers sense the output voltage at the VS pin of the flyback controller (Figure 1-1) and will adjust an internal control voltage (V_CL) to adjust the primary peak current (I_PP) and the converters switching frequency (f_SW). This control technique is known as control law. The control law of the UCC28704 is presented in Figure 2-1. All of the devices presented in this paper use similar control laws but are parametrically different. It is required that the designer review the data sheet of the specific flyback controller they are using in their design for specific control law details.

When the converter operates at maximum load and at the minimum input voltage the application operates in critical conduction at the converter's maximum switching frequency, (fsw(max)).

When the converter operates in region 4 if less duty cycle is required, the internal feedback amplifier will adjust V_CL from 4.85 V to 3.0 V to decrease f_SW to obtain the correct duty cycle to maintain V_OUT. The f_SW will be adjusted from f_SW(max) to 25 kHz minimum in region 4.

In region 3 when the converter is operating at 25 kHz, the flyback controller will adjust the primary peak current (I_PP) amplitude to adjust the duty cycle. The peak current varies from the maximum programed I_PP to I_PP/4 to maintain the duty cycle. The device adjusts V_CL from 3 V to 2.2 V in this region.

In region 2 with the primary peak current controlled to I_PP/4 if the controller needs less duty cycle it decreases the switching from 25 kHz to control the duty cycle. In this region V_CL operates from 2.2 V to 1.3V.

In region 1 when V_CL is below 1.3 V the converter is operating at the minimum switching frequency and requires a pre-load resistor (R_PL) to maintain regulation.

Figure 2-1 Control Law of UCC28704

3 Input (V_IN) and Output (V_OUT) Voltage Sensing for UVLO and OVP Fault Protection

V_IN and V_OUT are sensed and measured across the auxiliary winding (V_AUX) that is used to provide power to the flyback controller (U1) while the transformer is being energized. Figure 3-1 shows the switching wave form of DCM flyback converter operating near critical conduction. In this figure DRV is the logic level of the flyback controllers gate driver and CS is the voltage measured across the current sense resistor (R_CS). When the transformer is being energized during the flyback FETs (Q_A) on-time (t_ON) V_IN can be measured directly across V_AUX. Refer to Equation 1, Figure 1-1, and Figure 3-1 for details.

Equation 1.

$V_{I N} ≅ (V_{A U X} \times \frac{N_{P}}{N_{A}})$

Figure 3-1 Aux, CS, and DRV Signals at Max Load Minimum Line Voltage

The flyback controller can sense V_OUT while the transformer is delivering energy after the flyback converters transformer leakage spike that occurs during the T_{LK_RESET} time period has dissipated during t_DMAG. Refer to Equation 2 and Figure 1-1 for details.

Equation 2.

$V_{O U T} ≅ (V_{A U X} \times \frac{N_{S}}{N_{A}})$

To prevent false measurements of V_OUT the flyback controllers discussed in this paper have a leading edge blanking circuit. The controllers do not sense V_OUT during pre-programed blanking time (T_{LK_RESET}). T_{LK_RESET} moves with loading. For example, at full load, the UCC28704 controller will not sense V_OUT for 3 us (T_{LK_RESET}). When operating in the AM band to control the duty cycle, the transformer primary peak current adjusts linearly from I_PP to I_PP/4 to control the duty cycle. When the UCC28704 is operating in the AM band T_{LK_RESET} will be adjusted from 3 µs down to 750 ns as the primary-peak current decreases. When this occurs the flyback converter will go deeper into DCM operation. Refer to Figure 3-2 for details. Please note for this aux winding to sense the V_OUT correctly requires the aux winding signal to be as clean as possible between the end of T_{LK_RESET} and the end of t_DMAG. This will be discussed in greater detail later in this application note.

Figure 3-2 V_AUX, CS, and DRV While the Flyback Operating Deep into DCM Operation

4 Input Under Voltage Lockout (UVLO) Protection

These flyback controllers have programmable input under voltage detection that can be set and adjusted primary to auxiliary turns ration and properly selecting R_S1 and R_S2Figure 1-1. Refer to the flyback controller data sheet for instructions on programming the input UVLO.

The VS pin of these flyback controllers have an internal clamp on the VS pin that clamps the VS pin to roughly ground (GND) while Q1 is on (t_ON), (Figure 3-1 and Figure 3-2). During this this time the current coming out of the VS pin (I_VSL) in combination with R_S1 and the N_P/N_A turns ratio will determine the input voltage level the flyback converter will start at (V_IN(run)) and what input voltage the converter will stop switching at (V_IN(stop)). The value I_VSL(run)start and I_VSL(stop) stop thresholds will vary based on the flyback controller that is used in the design, refer to the flyback controller data sheet for the correct values.

The design presented in Figure 1-1 does not start switching until V_IN is greater than 67 V and will stop switching when V_IN drops below 23.8 V. Refer to Equation 3 through Equation 6 for details.

Equation 3.

$I_{V S L (r u n)} = 225 µ A$ , VS line sensed run current

Equation 4.

$V_{I N (r u n)} \geq I_{V S L (r u n)} \times R_{S 1} \times \frac{N_{P}}{N_{A}} = 225 µ A \times 51.1 k Ω \times 5.83 = 67 V$ , V_IN startup threshold

Equation 5.

$I_{V S L (s t o p)} = 80 µ A$

Equation 6.

$V_{I N (s t o p)} < I_{V S L (s t o p)} \times R_{S 1} \times \frac{N_{P}}{N_{A}} = 80 µ A \times 51.1 k Ω \times 5.83 = 23.8 V$

When power is first applied to V_IN the VDD capacitor (C_DD) trickle charges through R_T of Figure 1-1. Note that some flyback controllers trickle charge the C_DD capacitor with an internal JFET startup circuit. The capacitor continues to trickle charge until the flyback controllers turn on threshold is reached (V_VDD(on)). At this point it will deliver 3 gate drivers pulse to sample V_IN and V_OUT at the controllers maximum switching frequency (f_SW(max)). The UCC28704 controls the primary current to I_PP(max) /4. At this point t_{LK_RESET} will be reduced to it's minimum blanking time of 750 ns. If the converter detects a UVLO and/or a OVP fault during this time, the gate driver stops switching and the I_DD current will discharge C_DD to the flyback controllers turnoff threshold (V_VDD(off)). After C_DD is discharged to V_VDD(off), C_DD will once again be charged through R_T until the VDD pin reaches V_VDD(on). At this point the controller will sample V_OUT and V_IN again. If the fault is cleared the flyback will continue to operate. If the fault is not cleared switching will stop and the C_DD capacitor will be discharged and charged between V_VDD(off) and V_VDD(on) until the fault is cleared.

Equation 7. V_VDD(on) = 21 V

Equation 8. V_VDD(off)= 8 V

Figure 4-1, shows an example of how the input fault protection operates with different input voltages. At the beginning of time interval t_A 50 V is applied at V_IN, the C_DD capacitor trickle charged up to V_VDD(on). The flyback controller samples the input through N_P/N_A turns ratio and will detect an input UVLO fault and stops switching. The controller enters fault mode operation during this time interval. At the beginning of time interval t_B the input voltage is increase to 120 V, however, the flyback controller is still not switching, it waits until C_DD is charge up to V_VDD(on) to gives three DRV pulses to sample the input voltage. At the beginning of time internal t_C the flyback controller based on input sampling is no longer in a UVLO condition and the flyback converter will continue switching. The C_DD capacitor will discharge down to the reflected output voltage determined by the N_A/N_S turns ratio, at this point the flyback controller will be powered by the auxiliary winding (N_A) of T1. At the beginning of time interval t_D the input voltage was removed from V_IN simulating a brown out condition. The input bulk capacitor C_IN discharges based on the loading on the output of the flyback converter. At the beginning of time interval t_E capacitor C_IN will have discharged to a point where the input voltage will cause a UVLO fault. The UVLO fault has to be sampled in three consecutive switching cycles before the flyback controller stop switching. The flyback controller will remain operating in this mode until an input voltage is applied to V_IN that causes the I_VLS current to be greater than I_VSL(run).

Figure 4-1 Example of UVLO Fault Detection

5 Output Overvoltage (OVP) Protection

These flyback controllers sense the output voltage on V_AUX through a resistor divider formed by R_S1 and R_S2 and flyback controller's sense pin (VS). If the VS pin exceeds the V_OVP threshold for three consecutive switching cycles the controller determines that an OVP event has occurred and gate driver switching stops.

Equation 9.

V_{O V P} = 4.6 V

Equation 10.

V_{O U T} \geq \frac{V_{O V P} \times (R_{S 1} + R_{S 2})}{R_{S 2}} \times \frac{N_{S}}{N_{A}}

The schematic in Figure 1-1 represents a flyback converter that was designed to step down an input voltage (V_IN) of 75 V to 390 V DC to a regulated 12 V, 10 W output. The N_S/N_A turns ratio used in this design was 1. In this example, the flyback converter shuts down if V_OUT for three consecutive switching cycles is greater than 13.6 V triggering OVP protection, Equation 11.

Equation 11.

V_{O U T} \geq \frac{4.6 V \times (26.1 k Ω + 51.1 k Ω)}{26.1 k Ω} \times 1 = 13.6 V

If an OVP fault is detected DRV switching stops and the C_DD capacitor is discharged down to V_VDD(off). The C_DD capacitor trickle charges through R_T until V_CDD reaches V_VDD(on). At this point the controller gives three DRV sample pulses at f_SW(max) controlling the primary current to I_PP(max) /4 and t_{LK_RESET} blanking is set to its minimum of 750 ns. Remember that VS will detect an OVP from the end of T_{LK_RESET}to the end of t_DMAG . Refer to Figure 3-1 and Figure 3-2 for details. The CDD and DRV behavior during an OVP fault behaves in similar to UVLO fault presented in Figure 4-1.

6 Not Recognizing a UVLO or OVP Fault

Some designers report that on their initial prototypes that flyback controllers using PSR fault sensing do not startup. They report either there are no gate drive pules and or VDD looks like a saw tooth presented in Figure 6-1. In this case, the flyback controller is only going into UVLO, OVP or OCP fault protection. When the fault is cleared, VDD will stop cycling between V_VDDon and V_VDDoff and the flyback resumes normal operation.

Figure 6-1 VDD Cycling During Between VDD(on) and VDD(off) Indicates a UVLO or OVP Fault

7 Separate Bias Supply Startup Issue and Resolution

When starting up a prototype flyback converter some engineers use a separate bias supply for powering VDD of the flyback controller. Some of these designers have mentioned that there are no gate driver pulses observed and the flyback controller appears to be not functioning. Most of the time the issue is when power was applied to VDD there was no input voltage applied to the flyback converter. The flyback converter had already sampled the input voltage and because there was none present the controller entered input UVLO fault protection. The gate driver stopped switching and the external bias supply is prevents cycling of the VDD pin between V_VDD(off), V_VDD(on) and V_VDD(off) to reset the fault.

To resolve this issue apply the input voltage to V_IN that is greater than the UVLO trip point. Then bring the bias voltage to VDD above V_VDD(on). The other option is adjust the bias voltage at VDD below V_VDD(off) and then above V_VDD(on) to reset and clear the UVLO fault.

8 Not Having a Clean Aux Winding Signal

The waveform in Figure 8-1 is a simulation of a flyback converters switch node (V_SW), the aux winding voltage (V_AUX), and the flyback current sense signal (V_CS) of a flyback converter that uses a TVS clamp and no provisions for dampening aux winding ringing. This simulation is based on the flyback converter presented in Figure 1-1 without the circuitry that was highlighted in green.

Figure 8-1 Noisy VAUX Falsely Trigger OVP and/or UVLO Fault Protection

The flyback converter was designed to trigger OVP when V_OUT and V_AUX were greater than 13.6 V. This flyback converter did not have any previsions for dampening the switch node (V_SW) ringing cause by parasitic inductance and capacitance at the switch node. The noise at V_SW is couple through the auxiliary to primary turns ratio (N_A/N_P) and will falsely trip OVP fault protection.

The flyback controller samples for an OVP (t_OVP) after T_{LK_RESET} has timed out to the end of the transformer demagnetizing time (t_DMAG). The waveform in Figure 8-1 shows the ringing on V_AUX is greater than 13.6 V during the over voltage protection sampling time (t_OVP). This ringing causes the design to shut down and not regulate the output voltage correctly.

The Vaux ringing in Figure 8-1 is excessive and rings down below ground during t_{LK_RESET}. This behavior is known to trigger a UVLO faults and shut down the converter. This is because when the VS pin crosses ground it activates input UVLO fault.