These flyback controllers sense the output voltage on VAUX through a resistor divider formed by RS1 and RS2 and flyback controller's sense pin (VS). If the VS pin exceeds the VOVP threshold for three consecutive switching cycles the controller determines that an OVP event has occurred and gate driver switching stops.
The schematic in Figure 1-1 represents a flyback converter that was designed to step down an input voltage (VIN) of 75 V to 390 V DC to a regulated 12 V, 10 W output. The NS/NA turns ratio used in this design was 1. In this example, the flyback converter shuts down if VOUT for three consecutive switching cycles is greater than 13.6 V triggering OVP protection, Equation 11.
If an OVP fault is detected DRV switching stops and the CDD capacitor is discharged down to VVDD(off). The CDD capacitor trickle charges through RT until VCDD reaches VVDD(on). At this point the controller gives three DRV sample pulses at fSW(max) controlling the primary current to IPP(max) /4 and tLK_RESET blanking is set to its minimum of 750 ns. Remember that VS will detect an OVP from the end of TLK_RESET to the end of tDMAG . Refer to Figure 3-1 and Figure 3-2 for details. The CDD and DRV behavior during an OVP fault behaves in similar to UVLO fault presented in Figure 4-1.