The waveform in Figure 8-1 is a simulation of a flyback converters switch node (VSW), the aux winding voltage (VAUX), and the flyback current sense signal (VCS) of a flyback converter that uses a TVS clamp and no provisions for dampening aux winding ringing. This simulation is based on the flyback converter presented in Figure 1-1 without the circuitry that was highlighted in green.
The flyback converter was designed to trigger OVP when VOUT and VAUX were greater than 13.6 V. This flyback converter did not have any previsions for dampening the switch node (VSW) ringing cause by parasitic inductance and capacitance at the switch node. The noise at VSW is couple through the auxiliary to primary turns ratio (NA/NP) and will falsely trip OVP fault protection.
The flyback controller samples for an OVP (tOVP) after TLK_RESET has timed out to the end of the transformer demagnetizing time (tDMAG). The waveform in Figure 8-1 shows the ringing on VAUX is greater than 13.6 V during the over voltage protection sampling time (tOVP). This ringing causes the design to shut down and not regulate the output voltage correctly.
The Vaux ringing in Figure 8-1 is excessive and rings down below ground during tLK_RESET. This behavior is known to trigger a UVLO faults and shut down the converter. This is because when the VS pin crosses ground it activates input UVLO fault.