These flyback controllers have programmable input under voltage detection that can be set and adjusted primary to auxiliary turns ration and properly selecting RS1 and RS2Figure 1-1. Refer to the flyback controller data sheet for instructions on programming the input UVLO.
The VS pin of these flyback controllers have an internal clamp on the VS pin that clamps the VS pin to roughly ground (GND) while Q1 is on (tON), (Figure 3-1 and Figure 3-2). During this this time the current coming out of the VS pin (IVSL) in combination with RS1 and the NP/NA turns ratio will determine the input voltage level the flyback converter will start at (VIN(run)) and what input voltage the converter will stop switching at (VIN(stop)). The value IVSL(run) start and IVSL(stop) stop thresholds will vary based on the flyback controller that is used in the design, refer to the flyback controller data sheet for the correct values.
When power is first applied to VIN the VDD capacitor (CDD) trickle charges through RT of Figure 1-1. Note that some flyback controllers trickle charge the CDD capacitor with an internal JFET startup circuit. The capacitor continues to trickle charge until the flyback controllers turn on threshold is reached (VVDD(on)). At this point it will deliver 3 gate drivers pulse to sample VIN and VOUT at the controllers maximum switching frequency (fSW(max)). The UCC28704 controls the primary current to IPP(max) /4. At this point tLK_RESET will be reduced to it's minimum blanking time of 750 ns. If the converter detects a UVLO and/or a OVP fault during this time, the gate driver stops switching and the IDD current will discharge CDD to the flyback controllers turnoff threshold (VVDD(off)). After CDD is discharged to VVDD(off), CDD will once again be charged through RT until the VDD pin reaches VVDD(on). At this point the controller will sample VOUT and VIN again. If the fault is cleared the flyback will continue to operate. If the fault is not cleared switching will stop and the CDD capacitor will be discharged and charged between VVDD(off) and VVDD(on) until the fault is cleared.
Figure 4-1, shows an example of how the input fault protection operates with different input voltages. At the beginning of time interval tA 50 V is applied at VIN, the CDD capacitor trickle charged up to VVDD(on). The flyback controller samples the input through NP/NA turns ratio and will detect an input UVLO fault and stops switching. The controller enters fault mode operation during this time interval. At the beginning of time interval tB the input voltage is increase to 120 V, however, the flyback controller is still not switching, it waits until CDD is charge up to VVDD(on) to gives three DRV pulses to sample the input voltage. At the beginning of time internal tC the flyback controller based on input sampling is no longer in a UVLO condition and the flyback converter will continue switching. The CDD capacitor will discharge down to the reflected output voltage determined by the NA/NS turns ratio, at this point the flyback controller will be powered by the auxiliary winding (NA) of T1. At the beginning of time interval tD the input voltage was removed from VIN simulating a brown out condition. The input bulk capacitor CIN discharges based on the loading on the output of the flyback converter. At the beginning of time interval tE capacitor CIN will have discharged to a point where the input voltage will cause a UVLO fault. The UVLO fault has to be sampled in three consecutive switching cycles before the flyback controller stop switching. The flyback controller will remain operating in this mode until an input voltage is applied to VIN that causes the IVLS current to be greater than IVSL(run).