ZHDA202 June   2026 TAC5212

 

  1.   1
  2.   多 TAC5x1x 器件,带共享 TDM 和 I2C 总线
  3.   商标
  4. 1简介
  5. 2共享控制总线
  6. 3共享音频总线
    1. 3.1 共享 TDM 的 ASI 配置
    2. 3.2 菊花链 TDM 的 ASI 配置
  7. 4为多个 TAC5x1x EVM 配置 PurePath Console 3
    1. 4.1 更改 TAC5x1x 的默认 I2C 地址
    2. 4.2 启动 PurePath Console(针对多个器件)
  8. 5PurePath Console I2C 脚本
    1. 5.1 用于共享 TDM 的 TAC5x1x I2C 脚本
    2. 5.2 用于菊花链 TDM 的 TAC5x1x I2C 脚本

用于菊花链 TDM 的 TAC5x1x I2C 脚本

以下 I2C 脚本在器件复位后将四个器件设置为菊花链 TDM 模式:

# Key: w NN YY ZZ ==> write to I2C address 0xNN, to register 0xYY, data 0xZZ
#               # ==> comment delimiter
#
# I2C programming script for four devices in daisy chain TDM mode
#  U4(DOUT) -> (GPIO1) U3 (DOUT) -> (GPIO1) U2 (DOUT) -> (GPIO1) U1 (DOUT) -> Host Processor
#
#########################################################################
# Power-up Sequence:
# Power up IOVDD and AVDD power supplies
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Wait for 2ms.
#########################################################################
# Wake-up devices
w A0 02 09  # Wake-up Device U1
w A2 02 09  # Wake-up Device U2
w A4 02 09  # Wake-up Device U3
w A6 02 09  # Wake-up Device U4
d 10        # 10 ms delay
# Program Device A (U1), interfaces to host processor
w A0 00 00  # Set Device page register to Page 0 
w A0 1A 30  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity
w A0 1B 60  # ASI transmit Hi-Z for unused cycles 
w A0 18 49 # Set U1's ASI to daisy chain via GPIO1 
w A0 21 10 # Set U1's GPIO1 input as ASI input for daisy chain
w A0 1E 20 # Set U1 Ch1 mapped to slot 0 of DOUT 
w A0 1F 21 # Set U1 Ch2 mapped to slot 1 of DOUT 
w A0 20 22 # Set U1 Ch3 mapped to slot 2 of DOUT 
w A0 21 23 # Set U1 Ch4 mapped to slot 3 of DOUT
w A0 76 F0  # Enable Ch1-4 of Device A
# Program Device B (U2)
w A2 00 00  # Set Device page register to Page 0 
w A2 1A 30  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity
w A2 1B 60  # ASI transmit Hi-Z for unused cycles 
w A2 18 49 # Set U2's ASI to daisy chain via GPIO1 
w A2 21 10 # Set U2's GPIO1 input as ASI input for daisy chain
w A2 1E 20 # Set U2 Ch1 mapped to slot 0 of DOUT 
w A2 1F 21 # Set U2 Ch2 mapped to slot 1 of DOUT 
w A2 20 22 # Set U2 Ch3 mapped to slot 2 of DOUT 
w A2 21 23 # Set U2 Ch4 mapped to slot 3 of DOUT 
w A2 76 F0  # Enable Ch1-4 of Device B
# Program Device C (U3)
w A4 00 00  # Set Device page register to Page 0 
w A4 1A 30  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity
w A4 1B 60  # ASI transmit Hi-Z for unused cycles 
w A4 18 49 # Set U3's ASI to daisy chain via GPIO1 w A4 21 10 # Set U3's GPIO1 input as ASI input for daisy chain 
w A4 1E 20 # Set U3 Ch1 mapped to slot 0 of DOUT 
w A4 1F 21 # Set U3 Ch2 mapped to slot 1 of DOUT 
w A4 20 22 # Set U3 Ch3 mapped to slot 2 of DOUT 
w A4 21 23 # Set U3 Ch4 mapped to slot 3 of DOUT
w A4 76 F0  # Enable Ch1-4 of Device C
# Program Device D (U4)
w A6 00 00  # Set Device page register to Page 0 
w A6 1A 30  # ASI Format TDM with 32-bit word length, default FSYNC and BCLK polarity
w A6 1B 60  # ASI transmit Hi-Z for unused cycles 
w A6 1E 20 # Set U4 Ch1 mapped to slot 0 of DOUT 
w A6 1F 21 # Set U4 Ch1 mapped to slot 1 of DOUT 
w A6 20 22 # Set U4 Ch1 mapped to slot 2 of DOUT 
w A6 21 23 # Set U4 Ch1 mapped to slot 3 of DOUT
w A6 76 F0  # Enable Ch1-4 of Device D
# Power-up Devices A, B, C, & D
w A0 78 C0  # Power up ADC and DAC of Device A
w A2 78 C0  # Power up ADC and DAC of Device B
w A4 78 C0  # Power up ADC and DAC of Device C
w A6 78 C0  # Power up ADC and DAC of Device D