ZHCU772 December   2021

 

  1.   说明
  2.   资源
  3.   特性
  4.   应用
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 支持资源
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

1.1 Key System Level Specifications

The objective of this reference design is to demonstrate the high-speed clocking solution for multichannel RF sampling transceiver signal chains. This design focuses on measuring the synchronization performance of the two AFE7950EVM devices along with their SNR, SFDR, and IMD3 performance. The data generation and data capture are done by the TSW14J56EVM, which is interfaced with AFE7950EVM using an FMC adapter card. Table 1-1 lists the key system level specifications for the multichannel signal chains from the clocking solution perspective.

Table 1-1 Key Specifications
Parameter Specification Condition Unit
SFDR AFE79xx sampling freq - 8847.36 M with 18 × interpolation, Spur free dynamic range 0-fDAC/2, –0.5 dBFS;
850 50.8 dBc
1800 51.9 dBc
2600 42 dBc
3500 44 dBc
4900 46.1 dBc
8100 46.1 dBc
SFDR AFE79xx sampling freq - 8847.36 M with 18x interpolation, Spur free dynamic range within 500 MHz fOUT ±250 MHz, –0.5 dBFS;
850 68.5 dBc
1800 79.4 dBc
2600 77 dBc
3500 75 dBc
4900 76 dBc
8100 75 dBc
IMD3 AFE79xx sampling freq - 8847.36M with 18x interpolation, 2 tones at ±10 MHz –13 dBFS each tone
850 MHz ±10 MHz –66 dBc
1800 MHz ±10 MHz

–63

 dBc
2600 MHz ±10 MHz –62 dBc
3500 MHz ±10 MHz

–61

 dBc
4900 MHz ±10 MHz –57 dBc
Channel-to-Channel Skew

AFE79xx sampling freq - 8847.36M with 18x interpolation, Using TSW14J56 EVMs in primary & secondary mode

 ps
850 5 ps
1800 5 ps
2600 5 ps
SNR AFE79xx sampling freq - 2949.12M with Decimation by 6, specs from SNR plots in the data sheet; Signal to noise ratio, –3 dBFs input signal;
840 63.2 dBFs
1750 60.9 dBFs
2610 62.5 dBFs
3700 62.2 dBFs
4910 60 dBFs

Channel-to-Channel Skew
SFDR AFE79xx sampling freq - 2949.12M with Decimation by 6, specs from data sheet; SFDR, –3 dBFs input signal;
840 88.2 dBFs
1750 80.6 dBFs
2610 88 dBFs
3700 84 dBFs
4910 78.9 dBFs

Channel-to-Channel Skew

AFE79xx sampling freq - 2949.12 M with Decimation by 12, Signal to noise ratio, –3 dBFs input signal; Using TSW14J56 EVMs in primary and secondary mode
840 5 ps
1750 5 ps
2610 5 ps
3700 5 ps
4910 5 ps