ZHCU772 December   2021

 

  1.   说明
  2.   资源
  3.   特性
  4.   应用
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 支持资源
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

LMX2820

The LMX2820 is a high-performance, wideband RF PLL with integrated VCO that supports a frequency range from 45 MHz to 22.6 GHz. The VCO operates from 5.65 GHz to 11.3 GHz, it uses the internal doubler to generate frequency up to 22.6 GHz. The device supports both fractional-N and integer-N modes, with a 32-bit fractional divider allowing fine frequency selection. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency goes up to 300 MHz in fractional mode or 400 MHz in integer mode and can attain very low in-band noise and integrated jitter. Its integrated RMS jitter of 36-fs for a 6-GHz output makes the device an ideal low-noise source. The device accepts input reference frequency up to 1.4 GHz, which combined with frequency dividers and programmable low-noise multiplier allows flexible frequency planning. The high speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. The additional programmable low-noise multiplier lets users mitigate the impact of integer boundary spurs. In fractional-N mode, the device can adjust the output phase by a 32-bit resolution. For applications that need fast frequency changes, the device supports an ultra-fast VCO calibration option, which takes around 2.5 μs. The LMX2820 adds support for generating or repeating SYSREF (compliant to JESD204B standard) making it an ideal low-noise clock source for high-speed data converters. The LMX2820 SYSREF fine delay adjustment is provided in this configuration to account for delay differences of board traces. This device uses a single 3.3-V supply and it has integrated LDOs that eliminate the need for onboard low-noise LDOs.