ZHCU772 December   2021

 

  1.   说明
  2.   资源
  3.   特性
  4.   应用
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 支持资源
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

2.3.2 AFE7950 Transmitter Performance

Table 2-3 shows the measured transmitter performance results in terms of SFDR and IMD3 for 2x2TX_44210 mode and an interpolation factor of 18. Measured SFDR and IMD3 of the AFE7950 with the proposed TIDA-010230 clocking solution are improved from the AFE7950EVM using the internal PLL clocks and is comparable with the external clock source from the signal generator.

Table 2-3 Transmitter Performance
Parameters Conditions Unit AFE7950
Data Sheet Specifications		 TIDA-010230 Measured AFE7950EVM Measured (INT CLK) AFE7950EVM Measured (EXT CLK)
SFDR For 0-FDAC/2 BW, DSA – 0 dB, –1 dBFS;
850 MHz dBc 50.8 34.35 33.98 34.1
1800 MHz dBc 51.9 45.21 44.15 45.15
2600 MHz dBc 42 45.17 40.3 45.48
3500 MHz dBc 44 45.94 43.95 42.4
4900 MHz dBc 46.1 39.62 39.3 39.12
8100 MHz dBc 46.1 29.3 29 30.05
SFDR For Fout ±250 MHz BW, DSA – 0 dB, –1 dBFS;
850 MHz dBc 68.5 72.64 72.09 72.92
1800 MHz dBc 79.4 70.66 67.91 71.19
2600 MHz dBc 77 71.3 68.3 68.96
3500 MHz dBc 75 70.12 65.73 68.11
4900 MHz dBc 76 67.44 62 62.67
8100 MHz dBc 75 59.9 60.55 60.63
IMD3 IMD3 for ±10 MHz tone offset, DSA – 0dB, –13 dBFS each tone
850 MHz ±10 MHz dBc –74.4 –70.65 –53.35 –55.43
1800 MHz ±10 MHz dBc –71.1 –75.7 –78.96 –79.01
2600 MHz ±10 MHz dBc –73 –72.28 –73.33 –72.42
3500 MHz ±10 MHz dBc –72 –71.95 –73.94 –72.35
4900 MHz ±10 MHz dBc –67.8 –65.32 –61.54 –62.94
8100 MHz ±10 MHz dBc –76.24 –73.94 –73.57