ZHCSNG6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

IPC Pin (Intelligent Power Control Pin)

Under certain conditions, the IPC pin provides a 50-µA current from an internal source (IIPC(SBP2)) which is controlled by logic as shown in Figure 7-9. The voltage on the VS pin is sampled during the demagnetization time to obtain an indication of the reflected output voltage (NVO). When the VS-pin voltage is lower than the 2.4-V lower LV mode threshold (VVSLV(LR)), the LOW_NVO logic signal is pulled high, and the current source is enabled during the run state of all normal control modes (SBP1, SBP2, LPM, ABM, and AAM).

When the sampled VS-pin voltage is higher than the 2.5-V upper LV mode threshold (VVSLV(UP)), the LOW_NVO logic signal becomes low. In the LOW_NVO = 0 V case, the 50-µA current source is enabled in the run state of SBP2 mode only.

To minimize stand-by power, the 50-µA source is always disabled during the wait state of any control mode. Additionally, if VVDD falls lower than the 13-V survival-mode threshold, the INT_STOP logic signal is pulled high and the current source is disabled during survival mode operation, irrespective of the VVS level.

GUID-DC33196D-44F9-4F65-B032-846C410E24B1-low.gif Figure 7-9 Control Circuit Diagram to the IPC-Pin Current Source

The multi-function IPC pin can be programmed to obtain one or more of the following benefits:

  1. Reduction of input power for special light-load and stand-by conditions
  2. Improvement of light-load efficiency at lower output voltages, such as 5 V and 9 V
  3. Reduction of burst-mode output ripple at lower output voltages
  4. Reduction of the over-power limit at lower output voltages
  5. Power management of a PFC controller, together with the S13 pin

To implement the benefit No. 1, connect a resistor RIPC from IPC pin to AGND pin. The 50-µA current source establishes a voltage (VIPC) across RIPC to program an increase in the CS-pin peak primary current threshold at very light loads. The transfer function between VIPC and the CS threshold (VCST_IPC) in SBP2 mode is illustrated in Figure 7-10.

Proper sizing of RIPC to AGND can further reduce the burst frequency in SBP2 for so-called tiny-load power and for stand-by power.

When VIPC is less than 0.9 V (or IPC is shorted to AGND), VCST_IPC threshold stays at the minimum level of 0.15 V. When VIPC is set between 0.9 V and 1.8 V, VCST_IPC is clamped at 0.27 V. For VIPC between 1.8 V and 3.8 V, there is a linear programmable VCST_IPC range between 0.27 V and 0.4 V. When VIPC is greater than 3.8 V, VCST_IPC remains clamped to 0.4 V. Be aware that high settings of VCST_IPC may, in some cases, introduce higher output ripple in deep light-load condition or provoke audible noise.

GUID-D86F7178-E930-4798-AA5C-C6D9BA05D62B-low.gifFigure 7-10 IPC Transfer Function to Program the SBP2 Peak Current Threshold

Because the enable status of the IPC current source contains the very useful output voltage information from the LOW_NVO logic state, the IPC pin can be used to further optimize power stage performance over a wide output voltage range. To gain benefits No.2, No. 3, and No. 4 of the IPC function, connect RIPC between the IPC pin and the CS pin, so that the current source can create additional CS-pin offset voltage on ROPP when VVS < 2.4 V. With higher CS offset, the operating range of the VCST signal will be higher than the actual power stage peak current. This forces the controller to operate in AAM mode for a wider actual output load range, and forces the burst-mode threshold down to a lower power level.

Figure 7-11 shows the side effect of the IPC-to-CS connection if the RIPC setting is the same. Because the controller enables 50 µA in the run state of SBP2, the lower peak magnetizing current of the IPC-to-CS connection makes the SBP2 burst frequency higher and results in weakening the stand-by power improvement. Therefore, a higher RIPC is needed to increase VCST_IPC to compensate the peak current change.

GUID-9EC118BA-4A95-4F13-B4F5-EF32DBF2EFE0-low.gifFigure 7-11 Effect of the CS-pin Offset Voltage from the IPC Pin

For benefit No. 5, the IPC pin can also be used to disable a PFC controller (if used) at all load conditions for lower voltage outputs to further improve the light-load efficiency . As shown in Power Management Function for a GaN Power IC and PFC Controller, the diode DIPC in series with RIPC is placed between IPC and CS pins, and VIPC established at IPC is used to drive a small-signal switch QIPC to disable the PFC controller such as UCC28056.

When VIPC is higher than its threshold voltage, QIPC can pull low the COMP pin voltage of a PFC controller, so its switching is disabled. As a consequence, PFC output voltage drops from the typical 400-V regulation level to the peak value of the AC line. This lowers the bulk voltage, which reduces the ZVS energy, which increases power stage efficiency for low voltage outputs. Furthermore, the power loss of the PFC power stage is out of the efficiency equation. One design example for those components are CS13(ZVSF) = 22 nF, CS13(PFC) = 0.22 µF, CIPC = 10 nF, RIPC = 69.8 kΩ, RIPC2 = 10 MΩ, and RIPC3 = 20 kΩ. Choose QIPC with threshold voltage less than 1.5 V to ensure that VIPC is sufficient to achieve low on-resistance (RDS(on)) even at very low burst frequencies.