ZHCSNG6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

Calculation of Compensation Network

The UCC28781-Q1 integrates two control concepts to benefit high-efficiency operation: peak current-mode control and burst-ripple control. The peak current loop in AAM can be analyzed based on linear control theory, so the compensation target is to obtain enough phase margin and gain margin for the given small-signal characteristic of a zero-voltage switching flyback converter. For transition-mode operation, the power stage can be modeled as a voltage-controlled current source charging an output capacitor (CO) with an equivalent-series resistance (RCo) and the output load (RO) as shown in Figure 8-2. The first-order plant characteristic and high switching frequency operation in AAM make the peak current loop easier to stabilize than when in ABM.

Figure 8-2 Small-Signal Model of ZVSF in AAM Loop

The adaptive burst mode (ABM) uses ripple-based control, so the linear control theory for AAM cannot be applied. As illustrated in Figure 7-4, the internal ramp compensation feature of the controller stabilizes the ABM control loop, so the external compensation network can be simplified.

Figure 8-3 Compensation Network, Hv(s)

The transfer function from IFB to VO guides the pole/zero placement of the general secondary-side compensation network in Figure 8-3. In the primary-side control circuitry, two poles at ωFB and ωOPTO introduce phase-delay on IFB. ωFB pole is formed by the external filter capacitor CFB and the parallel resistance of the internal RFBI and the external current-limiting resistor (RFB). ωOPTO pole is formed by the parasitic capacitance of the optocoupler output (COPTO) and the series resistance of RFBI and RFB. For CFB = 220 pF, RFBI = 8 KΩ, and RFB = 20 KΩ, the delay effect of ωFB pole located at 139 kHz is negligible. COPTO is in the range of a few nanoFarads contributed by the Miller effect of the collector-to-base capacitance of the BJT in the optocoupler output, so ωOPTO pole is located at less than 10 kHz.

If the control loop bandwidth needs to be designed at higher frequency for a faster transient response, the phase delay effect of ωOPTO on the stability margin must be taken into account. Therefore, an RC network (RDIFF and CDIFF) in parallel with RBIAS1 is used to compensate the phase-delay of the optocoupler, which introduces an extra pole/zero pair located at ωP1 and ωZ1 respectively. The basic design guide is to place the ωZ1 zero close to the ωOPTO pole, and to place ωP1 pole away from highest fBUR. On the other hand, if the stability margin and transient response are sufficient to meet the requirements without RDIFF and CDIFF, then these two components are optional for the controller.

Equation 46. GUID-9B769C9E-EC65-4A2B-BAB3-E1F6CB142DCB-low.gif
Equation 47. GUID-15EBE2D9-7298-46C5-AC3D-8D86DFB7324C-low.gif
Equation 48. GUID-5DFB769C-4935-475E-A078-542492DEE55E-low.gif
Equation 49. GUID-EE1894EA-C6C9-44BD-85D5-69BD68C792B7-low.gif
Equation 50. GUID-B445F295-7227-4F71-8C4D-A0FF13B364AD-low.gif
Equation 51. GUID-5EF7A81A-BBE9-446D-BDEE-FC3F18B67658-low.gif

The step-by-step design procedure of the compensator without RDIFF and CDIFF is:

  1. RFB selection needs to consider both the output voltage regulation and compensation challenge on the low-frequency pole at ωOPTO. RFB should be less than the maximum value of 28 kΩ to provide a sufficient feedback current of 95 μA for the output voltage regulation in SBP2 mode, under the worst-case VFB(REG) and RFBI. However, RFB = 28 kΩ and COPTO = 2 nF result in an ωOPTO pole located at 2.8 kHz. This low-frequency pole may reduce phase margin at the cross-over frequency. If the control bandwidth is around this frequency range, RFB value should be designed even lower to move the pole to a higher frequency.
    Equation 52. GUID-CE57A666-58F4-42B0-BB38-75BBBD790B1C-low.gif
  2. RBIAS1 is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔVO(ABM), and target 4~5 μA of ΔIFB as example. At collector currents less than 100 μA, the CTR of most optocouplers can be as low as 10%, or 0.1 (used in this example), although some high performance devices can have higher CTR.
    Equation 53. RBIAS1=CTRIFB×VO(ABM)=0.15 μA×VO(ABM)
  3. RINT selection is not designed for the small-signal compensation, but to resolve the slow large-signal response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage continuously by the integrator configuration until the output voltage gets back to normal regulation level. If the load step-up transient happens before the output voltage is settled from the previous load step-down event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a new steady-state. Because the time for ATL431 to move from lower voltage to a high voltage delays iFB reduction, the controller response from SBP mode to AAM mode is delayed as well, which slows down the energy delivery to the output and results in a large voltage undershoot.
    To resolve this problem, RINT behaves like a current-limiting resistor for CINT, which slows down the reduction of the cathode voltage of ATL431. RINT needs to be adjusted based on the voltage undershoot requirement under the highest repetitive rate of load change.