ZHCSNG6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

P13 and SWS Pins

The P13 pin provides a regulated voltage to the gate of the depletion-mode MOSFET (QS), enabling QS to serve both VVDD start-up and loss-less ZVS-sensing from the high-voltage switch node (VSW) through the SWS pin. During VVDD start-up, the UVLO circuit controls two power-path switches connecting SWS and P13 pins to VDD pin with two internal current-limit resistors (RDDS and RDDH), as shown in Figure 7-5. In this configuration, QS behaves as a current source to charge the VDD capacitor (CVDD). RDDS is set at 5 kΩ when VVDD < 1.8 V to limit the maximum fault current under a VDD short-to-GND condition. RDDS is reduced to 500 Ω when VVDD > 1.8 V to allow VVDD to charge faster. The maximum charge current (ISWS) is affected by RDDS, the external series resistance (RSWS) from SWS pin to QS, and the threshold voltage of QS (VTH(Qs)). ISWS can be calculated as

Equation 8. ISWS=VTH(Qs)RDDS+RSWS
GUID-595E12B6-C629-4A8F-A3EF-64313A8E3A96-low.gifFigure 7-5 Operation of the VDD Startup Circuit

After VVDD reaches VVDD(ON), the two power-path switches open the connections between SWS, P13, and VDD pins. At this point, a third power-path switch connects an internal 13-V regulator to the P13 pin for configuring QS to perform loss-less ZVS sensing. Because the QS gate is fixed at 13 V, when the drain pin voltage of QS becomes higher than the sum of QS threshold voltage (VTH(Qs)) and the 13-V gate voltage, QS turns off and the source pin voltage of QS can no longer follow the drain pin voltage change. This gate control method makes QS act as a high-voltage blocking device with the drain pin connected to VSW. When the controller is switching, whenever VSW is lower than 13 V, QS turns on and forces the source pin voltage to follow VSW, becoming a replica of the VSW waveform at the lower voltage level, as illustrated in Figure 7-6.

The limited window for monitoring the VSW waveform is sufficient for ZVS control of the UCC28781-Q1, since the ZVS tuning threshold (VTH(SWS)) is set at 8.5 V for VSET = 5 V and set at 4 V for VSET = 0 V. The 8.5-V threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial-ZVS condition using Si primary switches. On the other hand, performing full ZVS operation is more suitable with GaN primary switches. Using a 4-V threshold helps to compensate for sensing delay between VSW and the SWS pin.

The internal 13-V regulator requires a high-quality ceramic by-pass capacitor (CP13) between the P13 pin and AGND pin for noise filtering and providing compensation to the P13 regulator. The minimum CP13 value is 1 μF and an X7R-type dielectric capacitor with 25-V rating or better is recommended. The controller enters a fault state if the P13 pin is open or shorted to AGND during VVDD start-up, or if VP13 overshoot is higher than VP13(OV) of 15 V in run state. The output short-circuit current of P13 regulator (IP13(MAX)) is self-limited to approximately 130 mA.

Since the P13 pin interfaces to the external depletion-FET, during input surge or EFT testing the Cgd of the depletion-FET can inject charge into the P13 pin and may cause an over-voltage stress. Under such condition it is recommended to place an 18-V Zener diode (DP13) on the P13 pin to clamp its voltage below its abs-max level.

During AAM and ABM if the negative magnetizing current is large enough, a GaN device may operate in the reverse conduction condition before it turns on each switching cycle, so VSW may be around -5 V for a brief inteval and it appears on the SWS pin. The SWS-pin design of UCC28781-Q1 can sustain –6 V (continuous) and –10 V (transient) stress to enhance the robust operation of the GaN power stage.

During this interval, QS is in the on-state and its body diode may conduct for a short time when the voltage drop across the on-state resistance of QS is high enough. The external RSWS can limit the forward current flowing through the QS body diode, so the reverse recovery charge of the body diode can be significantly reduced. Too high of RSWS value weakens the start-up charge current of CVDD and results in a longer start-up time. RSWS can be expected be slightly higher than 500 Ω. A small back-to-back TVS across BSS126 gate-to-source should be added to protect the gate-to-source voltage from potential abnormal voltage stress. Ensure that the TVS clamping voltage is less than the BSS126 gate-to-source voltage rating but does not conduct below 15 V.

RSWS and a ceramic capacitor (CSWS) between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly. The delay is to ensure that the ZCD detection on the VS pin happens earlier than the ZVS detection on the SWS pin, such that the ZVS control can auto-tune the PWMH on-time in the proper direction. The minimum value of CSWS is 22 pF.

GUID-07BF464B-D67E-44DC-A1EA-6C355C049729-low.gifFigure 7-6 ZVS Sensing by Reusing the VDD Startup Circuit