• 符合面向汽车应用的 AEC-Q100 标准：
  • 温度等级 1，T_A：–40°C 至 125°C
  • 器件 HBM ESD 分类等级 2
  • 器件 CDM ESD 分类等级 C2A
• 提供功能安全
  • 可帮助进行功能安全系统设计的文档
• 开关频率：> 500 kHz
• 实现超过 93% 的峰值效率
• 实现小于 50mW 的待机功耗（基本系统）
• 零电压开关 (ZVS) 自适应控制和死区时间优化
• EMI 频率抖动，无需权衡瞬态响应或可闻噪声
• 具有内部补偿的可编程自适应突发模式 (ABM)
• 过热、过压、输出短路、过流、过功率和引脚故障保护
• 自动恢复故障响应
• 4 mm × 4 mm 24 引脚 QFN 封装

• 牵引逆变器
• 辅助偏置电源
• 便携式直流充电器
• 直流或交流充电（桩）站
• 直流/直流转换器

UCC28781-Q1 是一款零电压开关 (ZVS) 控制器，可用于超高开关频率，从而充分减小变压器尺寸并实现高功率密度。

该控制器采用直接同步整流器 (SR) 控制，可直接驱动 SR FET，充分提高效率并简化设计，因此无需独立 SR 控制器。（隔离式应用需要隔离式栅极驱动器 IC。）

ZVS 采用自适应死区时间控制，可有效降低开关损耗和 EMI。该设计使控制器在整个工作范围内具有极高转换效率。

可编程自适应突发模式 (ABM) 可灵活控制控制器进入和退出待机模式的时机，从而降低轻负载和空载待机功耗。ABM 还有助于减少纹波并有效降低可闻噪声。

该控制器提供多种具有自动重启（重试）响应功能的保护模式。

简化版应用

V_VDD = 20 V, R_RDM = 115 kΩ, R_RTZ = 140 kΩ, V_SET = 0 V, and T_J = T_A = 25 ⁰C (unless otherwise noted)

Figure 6-1 VDD Bias-Supply Current vs. VDD Bias-Supply Voltage

Figure 6-3 VS Line-Sense Currents vs. Temperature

Figure 6-5 CS Peak-Power Threshold for V_VS > V_VSLV(UP) vs. VS Line-Sense Currents

Figure 6-7 t_Z Compensation Ratio (K_TZ) vs. VS Line-Sense Currents

Figure 6-9 REF Voltage vs. Temperature

Figure 6-11 FLT OTP Thresholds vs. Junction Temperature

A.

Figure 6-13 Max. XCD Discharge Current vs. Junction Temperature

Figure 6-2 VDD Bias-Supply Current vs. Temperature

Figure 6-4 Percentage Variation of Maximum and Minimum CS Thresholds vs. Temperature

A.

Figure 6-6 CS Peak-Power Threshold for V_VS < V_VSLV(LR) vs. VS Line-Sense Currents

Figure 6-8 VS Over-Voltage Threshold vs. Temperature

Figure 6-10 P13 Voltage vs. Temperature

Figure 6-12 XCD Thresholds vs. Junction Temperature

The UCC28781-Q1 is a transition-mode zero-voltage-switching flyback (ZVSF) controller equipped with advanced control schemes to enable significant size reduction of passive components for higher power density and higher average efficiency. Its control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs in a single-switch flyback configuration at high frequencies. In burst mode at very light loads the switching frequency may increase up to 1.5 MHz.

The ZVSF control of the UCC28781-Q1 is capable of auto-tuning the on-time of a secondary-side synchronous rectifier switch (Q_SR) by using a unique lossless ZVS-sensing network connected between the switch-node voltage (V_SW) and the SWS pin. The ZVSF controller is designed to adaptively achieve targeted full-ZVS or partial-ZVS conditions for the primary-side main switch (Q_L) with minimum circulating energy over wide operating conditions. Auto-tuning eliminates the risk of losing ZVS due to component tolerance, temperature, and input/output voltage variations, since the Q_SR on-time is corrected cycle-by-cycle.

Dead-times between PWML (controls Q_L) and PWMH (controls Q_SR) are optimally adjusted to help minimize the circulating energy required for ZVS as operating conditions change. Therefore, the overall system efficiency is improved and more consistent in mass production of the soft-switching topology. The programming features of the RTZ, RDM, BUR, IPC, and SET pins provide rich flexibility to optimize the power stage efficiency across a range of output power and operating frequency levels.

The UCC28781-Q1 uses five different steady-state operating modes to maximize efficiency over wide load and line ranges:

1. At higher load levels, adaptive amplitude modulation (AAM) adjusts the peak primary current.
2. In the medium-load range, adaptive burst mode (ABM) modulates the pulse count of each burst packet.
3. In the light-load range, low power mode (LPM) reduces the peak primary current of each two-pulse burst packet.
4. During very light-load conditions, stand-by power mode 1 (SBP1) minimizes the power loss.
5. During no-load conditions, stand-by power mode 2 (SBP2) minimizes the power loss.

During the system transient events such as the output load step down and output voltage overshoots, V_VDD may be reduced close to the 10.5-V UVLO-off threshold. In such cases, a sixth non-steady-state mode called survival mode (SM) is triggered to maintain V_VDD above 13 V and to reduce the size of the hold-up VDD capacitor.

The switching frequency-dither function is active in AAM to help reduce conducted-EMI noise and allow EMI filter size reduction. The 23-kHz dithering pattern and magnitude are designed to avoid audible noise, minimize efficiency influence, and desensitize the effect of the output voltage feedback loop response effect on the EMI attenuation. The dither function at low line can be programmed into disable mode based on the brown-in voltage setting, so the option provides design flexibility to balance the worst-case low-line efficiency and EMI. The dither fading feature smoothly disables the dither signal when the output load is close to the transition point between AAM and ABM. The 23-kHz dither frequency is high enough to allow a higher control-loop bandwidth for improved load transient response without distorting the dither signal and impairing EMI.

The unique burst mode control in ABM, LPM, and two SBP modes maximizes the light-load efficiency of the ZVSF power stage while avoiding the concerns of conventional burst operation - such as high output ripple and audible noise. The internal ramp compensation can stabilize the burst control loop without an external compensation network. The burst control provides an enable signal through the RUN pin to dynamically manage the static current of the SR gate-driver and also adaptively disables the drive signal of Q_SR. The internal drivers of RUN and PWMH can supply and disconnect the 5-V bias voltage to a digital isolator through a small-signal diode. The disconnect switch inside the S13 pin can directly control the 13-V bias voltage to a low-side GaN driver. These power management functions with RUN, PWMH, and S13 pins can be used to minimize the quiescent power consumed by those devices during burst off time, further improving the converter’s light-load efficiency and reducing its stand-by power.

The S13 and IPC pins of the UCC28781-Q1 can be adapted to manage an upstream PFC stage to maximize the light-load efficiency of higher power applications. The S13 pin can supply a 13-V bias voltage to the PFC controller whenever the ZVSF controller is in the run state. The pin disconnects the bias voltage during the wait states of the burst mode operation. When the burst frequency is reduced in very light load conditions, the bias voltage will decay below UVLO and shut down PFC controller, so the power loss from PFC can be eliminated.

The PWML output is a strong driver for a Si power MOSFET with high capacitive loading, a GaN-based gate injection transistor (GIT) with continuous on-state current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped at 13 V to balance the conduction loss reduction and gate charge loss of Si MOSFET. A dedicated driver ground return pin (PGND) minimizes the parasitic impedance and noise coupling of the PWML gate-drive loop to achieve faster switching speed and reduced turn-off loss of Q_L. The short 15-ns propagation delay and narrow 110-ns minimum on-time enable more accurate ZVS control and higher switching frequency operation.

During initial power up or VDD restart, the ZVSF stops switching, so UCC28781-Q1 starts up the VDD supply voltage with an external high-voltage depletion-mode MOSFET between the ZVSF switch node and the SWS pin. Fast startup is achieved with low stand-by power overhead, compared with using the conventional high-voltage startup resistance to VDD. Moreover, the P13 pin biases the gate of the depletion-mode FET to also allow this MOSFET to be used in lossless ZVS-sensing. This arrangement avoids additional sensing devices.

The enhanced switching control of UCC28781-Q1 mitigates excessive drain-to-source voltage stress on a synchronous rectifier (SR) caused by temporary continuous conduction mode (CCM), so the power loss of an SR snubber can be reduced for higher efficiency. Additional PWML timing controls can avoid premature Q_L turn-on before the magnetizing current reaches to zero through an improved zero-crossing detection (ZCD) scheme of the VS pin.

The UCC28781-Q1 also integrates more robust protection features tailored to maximize system reliability and safety. These features include active X-capacitor discharge, internal soft start, brown in/out, output over-voltage (OVP), input line over-voltage (IOVP), output over-power (OPP), system over-temperature (OTP), switch over-current (OCP), output short-circuit protection (SCP), and pin faults. All fault responses are auto-recovery, which means that the controller will attempt to restart after the shut-down time elapses.

The X-capacitor discharge function can actively discharge the residual voltage on X2 safety capacitors to a safe level after AC-line voltage removal is detected through the XCD pins of UCC28781-Q1 and its external sensing circuit. If the AC-line voltage recovers within 2 seconds after the line removal, the controller will reset the fault state immediately and will attempt to restart without waiting to fully discharge the bulk input capacitor or VDD capacitor. Grounding the two XCD pins disables this function and eliminates the sensing circuit. Unlike other conventional flyback controllers, UCC28781-Q1 provides the design flexibility of using the X-capacitor discharge function based on application power level as it is decoupled from VDD startup and brown-in/out detection functions. Since those two functions are implemented on the SWS and VS pins, respectively, UCC28781-Q1 maintains the two functions even when the XCD-related components are fully removed.

The voltage at the BUR pin (V_BUR) sets a target peak current-sense threshold at the CS pin (V_CST(BUR)) which programs the onset of adaptive burst mode (ABM). V_BUR also determines the clamped peak current level of switching cycles in each burst packet. When V_BUR is set higher, ABM will start at heavier output load conditions with higher peak primary current, so the benefit is higher light-load efficiency but the side effect is larger burst-mode output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest load condition to enter ABM (I_o(BUR)) for both Si and GaN-based designs. The gain between V_BUR and V_CST(BUR) is a constant gain of K_BUR-CST, so setting V_CST(BUR) just requires properly selecting the resistor divider on the BUR pin formed by R_BUR1 and R_BUR2. V_BUR should be set between 0.7 V and 2.4 V. If V_BUR is less than 0.7 V, V_CST(BUR) holds at 0.7 V / K_BUR-CST. If V_BUR is higher than 2.4 V, V_CST(BUR) stays at 2.4 V / K_BUR-CST.

Equation 1.

In order to enhance the mode transition between ABM and LPM, a programmable offset voltage (ΔV_BUR(LPM)) is generated on top of the V_BUR setting in ABM through an internal 2.7-μA current source (I_BUR(LPM)), as shown in Figure 7-1. In ABM, V_BUR is set through the resistor voltage divider to fulfill the target average efficiency. On transition from ABM to LPM, I_BUR(LPM) is enabled in LPM and flows out of the BUR pin, so ΔV_BUR(LPM) can be programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

Equation 2.

Figure 7-1 Hysteresis Voltage Generation on BUR Pin

When V_BUR steps higher on transition into LPM, the initial peak magnetizing current in LPM is increased with larger energy per switching cycle in each burst packet. This increases the output voltage which forces higher feedback current to restore regulation. Higher feedback current causes UCC28781-Q1 to stay in LPM, forming a hysteresis effect. If ΔV_BUR(LPM) is designed too small, it is possible that mode toggling between LPM and ABM can occur resulting in audible noise. For that situation, ΔV_BUR(LPM) greater than 100 mV is recommended.

To minimize the effects of external noise coupling on V_BUR, a filter capacitor on the BUR pin (C_BUR) may be needed. C_BUR needs to be properly designed to minimize the delay in generating ΔV_BUR during mode transitions. It is recommended that C_BUR should be sized small enough to ensure ΔV_BUR(LPM) settles within 40 μs, corresponding to the burst frequency of 25 kHz in LPM (f_LPM). Based on three RC time constants, representing 95% of a settled steady-state value from a step response, the design guide for C_BUR is expressed as

Equation 3.

In order to enhance the mode transition between ABM and AAM, a programmable offset voltage (ΔV_BUR(AAM)) is generated to lower the V_BUR with an internal 5-μA pull-down current (I_BUR(AAM)), as shown in Figure 7-1. After transition from ABM to AAM, I_BUR(AAM) is enabled in AAM and flows into the BUR pin, so ΔV_BUR(AAM) is also programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

Equation 4.

When V_BUR reduces after transition to AAM, the initial peak magnetizing current in AAM is reduced with less energy per switching cycle, which forces controller to continu operating in AAM. If ΔV_BUR(AAM) is too small, it is possible that either mode toggling between ABM and AAM or low-frequency ABM burst packets less than 20 kHz can occur and result in audible noise concern. For that situation, ΔV_BUR(AAM) greater than 150 mV is recommended. In some power stage designs, LPM in hard switching condition may cover a wider output load current range, so the light-load efficiency in LPM may be lower than ABM with ZVS condition. Besides, the ABM-to-AAM mode transition may be affected potentially when the load current condition of LPM-to-ABM transition is too close to the load current condition of ABM-to-AAM transition.

In order to optimize the output load current range in LPM, lower V_BUR(ABM), smaller ΔV_BUR(LPM), larger R_OPP, and smaller C_CS help to reduce the peak magnetizing current in LPM. If the LPM energy needs to be further reduced but V_BUR in AAM is limited by the 0.7-V minimum programmable level, the optional application circuit in Figure 7-2 can be considered. When the output load current is reduced, duty cycle of each burst packet becomes smaller, so as the duty cycle of RUN-pin voltage. C_BUR is discharged by the RUN driver through the small-signal diode (D_BUR) and the current limit resistor (R_RUN). Proper selection of R_RUN value can further reduce V_BUR(ABM) when the load current is reduced close to the transition point from ABM to LPM. One example BUR-pin setting is R_BUR1 = 182 kΩ, R_BUR2 = 37.4 kΩ, C_BUR = 330 pF, and R_RUN = 20 kΩ.

Figure 7-2 Optional Application Circuit to Reduce V_BUR in LPM

The FB pin usually connects to the collector of an optocoupler output transistor through an external current-limiting resistor (R_FB). A maximum of 20 kΩ for R_FB is recommended. The feedback network of UCC28781-Q1 is shown in Figure 7-3. A high-quality ceramic by-pass capacitor between FB pin and REF pin (C_FB) is required for decoupling I_FB from switching noise interference. A minimum of 220 pF is recommended for C_FB . An internal 8-kΩ resistor (R_FBI) at the FB pin in conjunction with the external C_FB forms an effective low-pass filter. Section 8 provides a detailed design guide on the secondary-side compensation network of V_O feedback loop, to improve the load transient response and also limit the I_FB ripple of ABM mode within the recommended range.

Figure 7-3 External Feedback Network Connected to the FB Pin

Depending on the operating mode, the controller interprets the current flowing out of the FB pin (I_FB) to regulate the output voltage. For AAM and LPM modes based on peak current control, I_FB is converted into an internal peak current-sense threshold (V_CST) to modulate the amplitude of the current-sense signal on the CS pin. For example, when the output voltage (V_O) is lower than the regulation level set by the shunt regulator, the absolute current level of I_FB reduces, causing a higher V_CST to increase more power to the output load. In ABM, the burst control loop takes over the V_O regulation, where V_CST is clamped to V_CST(BUR) and the ripple component of I_FB participates in the modulation of the burst off time.

Figure 7-4 illustrates the operating principle of the ABM. A burst of switching pulses raises the output voltage V_O which increases I_FB. At the end of the burst, the load current discharges the output capacitor, which decreases V_O and I_FB. UCC28781-Q1 injects a noise-free internal ramp compensation current (I_COMP) superimposed on I_FB in order to stabilize the ABM operation. When the RUN pin is high, I_COMP is reset to 0 μA. When the RUN pin goes low, I_COMP is gradually increased to 6 μA with a positive slope of 0.214 A/s. The summation of I_FB and I_COMP is compared with I_TH(FB) to trigger the next burst event. The magnitude and sharp slope of I_COMP help to push switching ripple and high-frequency noise component of I_OPTO away from I_TH(FB).

Figure 7-4 Concept of Burst Control with an Internal Ramp Compensation

The output of the internal 5-V regulator of the controller is connected to the REF pin. REF provides bias current to most of the functional blocks within the UCC28781-Q1. It requires a high-quality ceramic by-pass capacitor (C_REF) to AGND to decouple switching noise and to reduce the voltage transients as the controller transitions from wait state to run state. The minimum C_REF value is 0.22 μF, and a high quality dielectric material should be used, such as X7R.

The output short-circuit current (I_S(REF)) of the REF regulator is self-limited to approximately 17 mA. 5-V bias is only available after the under-voltage lock-out (UVLO) circuit enables the operation of UCC28781-Q1 when V_VDD reaches V_VDD(ON).

This pin can be used to perform an external shutdown function. A small-signal switch can be used to pull this pin voltage below the power-good threshold of 4.5V so the controller will stop switching, force a VDD restart cycle, and turn off the REF current.