该 AWR 器件是一款能够在 60GHz 至 64GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感器。该器件采用 TI 的低功耗 45nm RFCMOS 工艺制造,并且在超小封装中实现了出色的集成度。这是适用于汽车领域低功耗、自监控、超精确雷达系统的理想解决方案。当前提供多种符合汽车标准的型号,包括功能安全合规型器件和非功能安全器件。
器件型号 | 封装(1) | 封装尺寸 | 托盘/卷带包装 |
---|---|---|---|
AWR6843AQGABLRQ1 | FCBGA (161) | 10.4mm × 10.4mm | 卷带包装 |
AWR6843AQGABLQ1 | FCBGA (161) | 10.4mm × 10.4mm | 托盘 |
AWR6843ABGABLRQ1 | FCBGA (161) | 10.4mm × 10.4mm | 卷带包装 |
AWR6843ABGABLQ1 | FCBGA (161) | 10.4mm × 10.4mm | 托盘 |
AWR6843ABSABLRQ1 | FCBGA (161) | 10.4mm × 10.4mm | 卷带包装 |
AWR6843ABSABLQ1 | FCBGA (161) | 10.4mm × 10.4mm | 托盘 |
AWR6443ABGABLRQ1 | FCBGA (161) | 10.4mm × 10.4mm | 卷带包装 |
AWR6443ABGABLQ1 | FCBGA (161) | 10.4mm × 10.4mm | 托盘 |
图 4-1 展示了器件的功能方框图
Changes from April 2, 2021 to January 10, 2022 (from Revision C (April 2021) to Revision D (January 2022))
Unless otherwise noted, the device-specific information, in this document, relates to both the AWR6843 and AWR6443 devices. The device differences are highlighted in Table 5-1, Device Features Comparison.
FUNCTION | AWR6843AOP | AWR1843AOP | AWR6843(1) | AWR6443(1) | AWR1843 | AWR1642 | AWR1443 | |
---|---|---|---|---|---|---|---|---|
Antenna on Package (AOP) | Yes | Yes | — | — | — | — | — | |
Number of receivers | 4 | 4 | 4 | 4 | 4 | 4 | 4 | |
Number of transmitters | 3(2) | 3(2) | 3(2) | 3(2) | 3(2) | 2 | 3 | |
RF frequency range | 60 to 64 GHz | 76 to 81 GHz | 60 to 64 GHz | 60 to 64 GHz | 76 to 81 GHz | 76 to 81 GHz | 76 to 81 GHz | |
On-chip memory | 1.75MB | 2MB | 1.75MB | 1.4MB | 2MB | 1.5MB | 576KB | |
Max I/F (Intermediate Frequency) (MHz) | 10 | 10 | 10 | 10 | 10 | 5 | 5 | |
Max real sampling rate (Msps) | 25 | 25 | 25 | 25 | 25 | 12.5 | 12.5 | |
Max complex sampling rate (Msps) | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 | 6.25 | 6.25 | |
Device Security(3) | Yes | Yes | Yes | — | Yes | Yes | — | |
Processors | ||||||||
MCU (R4F) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
DSP (C674x) | Yes | Yes | Yes | — | Yes | Yes | — | |
Peripherals | ||||||||
Serial Peripheral Interface (SPI) ports | 2 | 2 | 2 | 2 | 2 | 2 | 1 | |
Quad Serial Peripheral Interface (QSPI) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
Inter-Integrated Circuit (I2C) interface | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Controller Area Network (DCAN) interface | — | 1 | — | — | 1 | 1 | 1 | |
Controller Area Network (CAN-FD) interface | 2 | 1 | 2 | 2 | 1 | — | — | |
Trace | Yes | Yes | Yes | Yes | Yes | Yes | — | |
PWM | Yes | Yes | Yes | Yes | Yes | Yes | — | |
Hardware In Loop (HIL/DMM) | Yes | Yes | Yes | Yes | Yes | Yes | — | |
GPADC | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
LVDS/Debug(4) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
CSI2 | — | — | — | — | — | — | — | |
Hardware accelerator | Yes | Yes | Yes | Yes | Yes | — | Yes | |
1-V bypass mode | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
JTAG | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
Product status | Product Preview
(PP), Advance Information (AI), or Production Data (PD) |
PD(5) | PD(5) | PD(5) | PD(5) | PD(5) | PD(5) | PD(5) |
For information about other devices in this family of products or related products see the links that follow.
Figure 6-1 shows the pin locations for the 161-pin FCBGA package. Figure 6-2, Figure 6-3, Figure 6-4, and Figure 6-5 show the same pins, but split into four quadrants.
All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.
The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.
SIGNAL NAME | PIN TYPE | DESCRIPTION | BALL NO. |
---|---|---|---|
BSS_UART_TX | O | Debug UART Transmit [Radar Block] | F14, H14, K13, N10, N13, N4, N5, R8 |
CAN1_FD_RX | I | CAN1 FD (MCAN) Receive Signal | D13, F14, N10, N4, P12 |
CAN1_FD_TX | O | CAN1 FD (MCAN) Transmit Signal | E14, H14, N5, P10, R14 |
CAN2_FD_RX | I | CAN2 FD (MCAN) Receive Signal | E13 |
CAN2_FD_TX | IO | CAN2 FD (MCAN) Transmit Signal | E15 |
DMM0 | I | Debug Interface (Hardware In Loop) - Data Line | R4 |
DMM1 | I | Debug Interface (Hardware In Loop) - Data Line | P5 |
DMM2 | I | Debug Interface (Hardware In Loop) - Data Line | R5 |
DMM3 | I | Debug Interface (Hardware In Loop) - Data Line | P6 |
DMM4 | I | Debug Interface (Hardware In Loop) - Data Line | R7 |
DMM5 | I | Debug Interface (Hardware In Loop) - Data Line | P7 |
DMM6 | I | Debug Interface (Hardware In Loop) - Data Line | R8 |
DMM7 | I | Debug Interface (Hardware In Loop) - Data Line | P8 |
DMM_CLK | I | Debug Interface (Hardware In Loop) - Clock | N15 |
DMM_MUX_IN | I | Debug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances) | G13, J13, P4 |
DMM_SYNC | I | Debug Interface (Hardware In Loop) - Sync | N14 |
DSS_UART_TX | O | Debug UART Transmit [DSP] | D13, E13, G14, P8, R12 |
EPWM1A | O | PWM Module 1 - Output A | N5, N8 |
EPWM1B | O | PWM Module 1 - Output B | H13, N5, P9 |
EPWM1SYNCI | I | J13 | |
EPWM2A | O | PWM Module 2- Output A | H13, N4, N5, P9 |
EPWM2B | O | PWM Module 2 - Output B | N4 |
EPWM2SYNCO | O | R7 | |
EPWM3A | O | PWM Module 3 - Output A | N4 |
EPWM3SYNCO | O | P6 | |
GPIO_0 | IO | General-purpose I/O | H13 |
GPIO_1 | IO | General-purpose I/O | J13 |
GPIO_2 | IO | General-purpose I/O | K13 |
GPIO_3 | IO | General-purpose I/O | E13 |
GPIO_4 | IO | General-purpose I/O | H14 |
GPIO_5 | IO | General-purpose I/O | F14 |
GPIO_6 | IO | General-purpose I/O | P11 |
GPIO_7 | IO | General-purpose I/O | R12 |
GPIO_8 | IO | General-purpose I/O | R13 |
GPIO_9 | IO | General-purpose I/O | N12 |
GPIO_10 | IO | General-purpose I/O | R14 |
GPIO_11 | IO | General-purpose I/O | P12 |
GPIO_12 | IO | General-purpose I/O | P13 |
GPIO_13 | IO | General-purpose I/O | H13 |
GPIO_14 | IO | General-purpose I/O | N5 |
GPIO_15 | IO | General-purpose I/O | N4 |
GPIO_16 | IO | General-purpose I/O | J13 |
GPIO_17 | IO | General-purpose I/O | P10 |
GPIO_18 | IO | General-purpose I/O | N10 |
GPIO_19 | IO | General-purpose I/O | D13 |
GPIO_20 | IO | General-purpose I/O | E14 |
GPIO_21 | IO | General-purpose I/O | F13 |
GPIO_22 | IO | General-purpose I/O | G14 |
GPIO_23 | IO | General-purpose I/O | R11 |
GPIO_24 | IO | General-purpose I/O | N13 |
GPIO_25 | IO | General-purpose I/O | N8 |
GPIO_26 | IO | General-purpose I/O | K13 |
GPIO_27 | IO | General-purpose I/O | P9 |
GPIO_28 | IO | General-purpose I/O | P4 |
GPIO_29 | IO | General-purpose I/O | G13 |
GPIO_30 | IO | General-purpose I/O | C13 |
GPIO_31 | IO | General-purpose I/O | R4 |
GPIO_32 | IO | General-purpose I/O | P5 |
GPIO_33 | IO | General-purpose I/O | R5 |
GPIO_34 | IO | General-purpose I/O | P6 |
GPIO_35 | IO | General-purpose I/O | R7 |
GPIO_36 | IO | General-purpose I/O | P7 |
GPIO_37 | IO | General-purpose I/O | R8 |
GPIO_38 | IO | General-purpose I/O | P8 |
GPIO_47 | IO | General-purpose I/O | N15 |
I2C_SCL | IO | I2C Clock | G14, N4 |
I2C_SDA | IO | I2C Data | F13, N5 |
LVDS_TXP[0] | O | Differential data Out – Lane 0 | J14 |
LVDS_TXM[0] | O | J15 | |
LVDS_TXP[1] | O | Differential data Out – Lane 1 | K14 |
LVDS_TXM[1] | O | K15 | |
LVDS_CLKP | O | Differential clock Out | L14 |
LVDS_CLKM | O | L15 | |
LVDS_FRCLKP | O | Differential Frame Clock | M14 |
LVDS_FRCLKM | O | M15 | |
MCU_CLKOUT | O | Programmable clock given out to external MCU or the processor | N8 |
MSS_UARTA_RX | I | Main Subsystem - UART A Receive | F14, N4, R11 |
MSS_UARTA_TX | O | Main Subsystem - UART A Transmit | H14, N13, N5, R4 |
MSS_UARTB_RX | IO | Main Subsystem - UART B Receive | N4, P4 |
MSS_UARTB_TX | O | Main Subsystem - UART B Transmit | F14, H14, K13, N13, N5, P10, P7 |
NDMM_EN | I | Debug Interface (Hardware In Loop) Enable - Active Low Signal | N13, N5 |
NERROR_IN | I | Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware | N7 |
NERROR_OUT | O | Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. | N6 |
PMIC_CLKOUT | O | Output Clock from AWR6843 device for PMIC | H13, K13, P9 |
QSPI[0] | IO | QSPI Data Line #0 (Used with Serial Data Flash) | R13 |
QSPI[1] | I | QSPI Data Line #1 (Used with Serial Data Flash) | N12 |
QSPI[2] | I | QSPI Data Line #2 (Used with Serial Data Flash) | R14 |
QSPI[3] | I | QSPI Data Line #3 (Used with Serial Data Flash) | P12 |
QSPI_CLK | O | QSPI Clock (Used with Serial Data Flash) | R12 |
QSPI_CLK_EXT | I | QSPI Clock (Used with Serial Data Flash) | H14 |
QSPI_CS_N | O | QSPI Chip Select (Used with Serial Data Flash) | P11 |
RS232_RX | I | Debug UART (Operates as Bus Master) - Receive Signal | N4 |
RS232_TX | O | Debug UART (Operates as Bus Master) - Transmit Signal | N5 |
SOP[0] | I | Sense On Power - Line#0 | N13 |
SOP[1] | I | Sense On Power - Line#1 | G13 |
SOP[2] | I | Sense On Power - Line#2 | P9 |
SPIA_CLK | IO | SPI Channel A - Clock | E13 |
SPIA_CS_N | IO | SPI Channel A - Chip Select | E15 |
SPIA_MISO | IO | SPI Channel A - Master In Slave Out | E14 |
SPIA_MOSI | IO | SPI Channel A - Master Out Slave In | D13 |
SPIB_CLK | IO | SPI Channel B - Clock | F14, R12 |
SPIB_CS_N | IO | SPI Channel B Chip Select (Instance ID 0) | H14, P11 |
SPIB_CS_N_1 | IO | SPI Channel B Chip Select (Instance ID 1) | G13, J13, P13 |
SPIB_CS_N_2 | IO | SPI Channel B Chip Select (Instance ID 2) | G13, J13, N12 |
SPIB_MISO | IO | SPI Channel B - Master In Slave Out | G14, R13 |
SPIB_MOSI | IO | SPI Channel B - Master Out Slave In | F13, N12 |
SPI_HOST_INTR | O | Out of Band Interrupt to an external host communicating over SPI | P13 |
SYNC_IN | I | Low frequency Synchronization signal input | P4 |
SYNC_OUT | O | Low Frequency Synchronization Signal output | G13, J13, K13, P4 |
TCK | I | JTAG Test Clock | P10 |
TDI | I | JTAG Test Data Input | R11 |
TDO | O | JTAG Test Data Output | N13 |
TMS | I | JTAG Test Mode Signal | N10 |
TRACE_CLK | O | Debug Trace Output - Clock | N15 |
TRACE_CTL | O | Debug Trace Output - Control | N14 |
TRACE_DATA_0 | O | Debug Trace Output - Data Line | R4 |
TRACE_DATA_1 | O | Debug Trace Output - Data Line | P5 |
TRACE_DATA_2 | O | Debug Trace Output - Data Line | R5 |
TRACE_DATA_3 | O | Debug Trace Output - Data Line | P6 |
TRACE_DATA_4 | O | Debug Trace Output - Data Line | R7 |
TRACE_DATA_5 | O | Debug Trace Output - Data Line | P7 |
TRACE_DATA_6 | O | Debug Trace Output - Data Line | R8 |
TRACE_DATA_7 | O | Debug Trace Output - Data Line | P8 |
FRAME_START | O | Pulse signal indicating the start of each frame | N8, K13, P9 |
CHIRP_START | O | Pulse signal indicating the start of each chirp | N8, K13, P9 |
CHIRP_END | O | Pulse signal indicating the end of each chirp | N8, K13, P9 |
WARM_RESET | IO | Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. | N9 |
INTERFACE | SIGNAL NAME | PIN TYPE | DESCRIPTION | BALL NO. |
---|---|---|---|---|
Transmitters | TX1 | O | Single ended transmitter1 o/p | B4 |
TX2 | O | Single ended transmitter2 o/p | B6 | |
TX3 | O | Single ended transmitter3 o/p | B8 | |
Receivers | RX1 | I | Single ended receiver1 i/p | M2 |
RX2 | I | Single ended receiver2 i/p | K2 | |
RX3 | I | Single ended receiver3 i/p | H2 | |
RX4 | I | Single ended receiver4 i/p | F2 | |
Reset | NRESET | I | Power on reset for chip. Active low | R3 |
Reference Oscillator | CLKP | I | In XTAL mode: Input for the reference crystal In External clock mode: Single ended input reference clock port | B15 |
CLKM | I | In XTAL mode: Feedback drive for the reference crystal In External clock mode: Connect this port to ground | C15 | |
Reference clock | OSC_CLKOUT | O | Reference clock output from clocking subsystem after cleanup PLL (1.4V output voltage swing). | A14 |
Bandgap voltage | VBGAP | O | Device's Band Gap Reference Output | B10 |
Power supply | VDDIN | Power | 1.2V digital power supply | H15, N11, P15, R6 |
VIN_SRAM | Power | 1.2V power rail for internal SRAM | G15 | |
VNWA | Power | 1.2V power rail for SRAM array back bias | P14 | |
VIOIN | Power | I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply | R10, F15 | |
VIOIN_18 | Power | 1.8V supply for CMOS IO | R9 | |
VIN_18CLK | Power | 1.8V supply for clock module | B11 | |
VIOIN_18DIFF | Power | 1.8V supply for LVDS port | D15 | |
VPP | Power | Voltage supply for fuse chain | L13 | |
Power supply | VIN_13RF1 | Power | 1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board | G5, H5, J5 |
VIN_13RF2 | Power | 1.3V Analog and RF supply | C2,D2 | |
VIN_18BB | Power | 1.8V Analog base band power supply | K5, F5 | |
VIN_18VCO | Power | 1.8V RF VCO supply | B12 | |
VSS | Ground | Digital ground | L5, L6, L8, L10, K7, K8, K9, K10, K11, J6, J7, J8, J10, H7, H9, H11, G6, G7, G8, G10, F9, F11, E5, E6, E8, E10, E11, R15 | |
VSSA | Ground | Analog ground | A1, A3, A5, A7, A9, A13, A15, B1, B3, B5, B7, B9, B14, C1, C3, C4, C5, C6, C7, C8, C9, C14, E1, E2, E3, F3, G1, G2, G3, H3, J1, J2, J3, K3, L1, L2, L3, M3, N1, N2, N3, R1 | |
Internal LDO output/inputs | VOUT_14APLL | O | Internal LDO output | A10 |
VOUT_14SYNTH | O | Internal LDO output | B13 | |
VOUT_PA | IO | Internal LDO output | A2, B2 | |
Test and Debug output for pre-production phase. Can be pinned out on production hardware for field debug | Analog Test1 / GPADC1 | IO | Analog IO dedicated for ADC service | P1 |
Analog Test2 / GPADC2 | IO | Analog IO dedicated for ADC service | P2 | |
Analog Test3 / GPADC3 | IO | Analog IO dedicated for ADC service | P3 | |
Analog Test4 / GPADC4 | IO | Analog IO dedicated for ADC service | R2 | |
ANAMUX / GPADC5 | IO | Analog IO dedicated for ADC service | C13 | |
VSENSE / GPADC6 | IO | Analog IO dedicated for ADC service | D14 |
BALL NUMBER [1] | BALL NAME [2] | SIGNAL NAME [3] | PINCNTL ADDRESS [4] | MODE [5][9] | TYPE [6] | BALL RESET STATE [7] | PULL UP/DOWN TYPE [8] |
---|---|---|---|---|---|---|---|
H13 | GPIO_0 | GPIO_13 | 0xFFFFEA04 | 0 | IO | Output Disabled | Pull Down |
GPIO_0 | 1 | IO | |||||
PMIC_CLKOUT | 2 | O | |||||
EPWM1B | 10 | O | |||||
ePWM2A | 11 | O | |||||
J13 | GPIO_1 | GPIO_16 | 0xFFFFEA08 | 0 | IO | Output Disabled | Pull Down |
GPIO_1 | 1 | IO | |||||
SYNC_OUT | 2 | O | |||||
DMM_MUX_IN | 12 | I | |||||
SPIB_CS_N_1 | 13 | IO | |||||
SPIB_CS_N_2 | 14 | IO | |||||
EPWM1SYNCI | 15 | I | |||||
K13 | GPIO_2 | GPIO_26 | 0xFFFFEA64 | 0 | IO | Output Disabled | Pull Down |
GPIO_2 | 1 | IO | |||||
OSC_CLKOUT | 2 | O | |||||
MSS_UARTB_TX | 7 | O | |||||
BSS_UART_TX | 8 | O | |||||
SYNC_OUT | 9 | O | |||||
PMIC_CLKOUT | 10 | O | |||||
CHIRP_START | 11 | O | |||||
CHIRP_END | 12 | O | |||||
FRAME_START | 13 | O | |||||
R4 | GPIO_31 | TRACE_DATA_0 | 0xFFFFEA7C | 0 | O | Output Disabled | Pull Down |
GPIO_31 | 1 | IO | |||||
DMM0 | 2 | I | |||||
MSS_UARTA_TX | 4 | IO | |||||
P5 | GPIO_32 | TRACE_DATA_1 | 0xFFFFEA80 | 0 | O | Output Disabled | Pull Down |
GPIO_32 | 1 | IO | |||||
DMM1 | 2 | I | |||||
R5 | GPIO_33 | TRACE_DATA_2 | 0xFFFFEA84 | 0 | O | Output Disabled | Pull Down |
GPIO_33 | 1 | IO | |||||
DMM2 | 2 | I | |||||
P6 | GPIO_34 | TRACE_DATA_3 | 0xFFFFEA88 | 0 | O | Output Disabled | Pull Down |
GPIO_34 | 1 | IO | |||||
DMM3 | 2 | I | |||||
EPWM3SYNCO | 4 | O | |||||
R7 | GPIO_35 | TRACE_DATA_4 | 0xFFFFEA8C | 0 | O | Output Disabled | Pull Down |
GPIO_35 | 1 | IO | |||||
DMM4 | 2 | I | |||||
EPWM2SYNCO | 4 | O | |||||
P7 | GPIO_36 | TRACE_DATA_5 | 0xFFFFEA90 | 0 | O | Output Disabled | Pull Down |
GPIO_36 | 1 | IO | |||||
DMM5 | 2 | I | |||||
MSS_UARTB_TX | 5 | O | |||||
R8 | GPIO_37 | TRACE_DATA_6 | 0xFFFFEA94 | 0 | O | Output Disabled | Pull Down |
GPIO_37 | 1 | IO | |||||
DMM6 | 2 | I | |||||
BSS_UART_TX | 5 | O | |||||
P8 | GPIO_38 | TRACE_DATA_7 | 0xFFFFEA98 | 0 | O | Output Disabled | Pull Down |
GPIO_38 | 1 | IO | |||||
DMM7 | 2 | I | |||||
DSS_UART_TX | 5 | O | |||||
N15 | GPIO_47 | TRACE_CLK | 0xFFFFEABC | 0 | O | Output Disabled | Pull Down |
GPIO_47 | 1 | IO | |||||
DMM_CLK | 2 | I | |||||
N14 | DMM_SYNC | TRACE_CTL | 0xFFFFEAC0 | 0 | O | Output Disabled | Pull Down |
DMM_SYNC | 2 | I | |||||
N8 | MCU_CLKOUT | GPIO_25 | 0xFFFFEA60 | 0 | IO | Output Disabled | Pull Down |
MCU_CLKOUT | 1 | O | |||||
CHIRP_START | 2 | O | |||||
CHIRP_END | 6 | O | |||||
FRAME_START | 7 | O | |||||
EPWM1A | 12 | O | |||||
N7 | NERROR_IN | NERROR_IN | 0xFFFFEA44 | 0 | I | Input | |
N6 | NERROR_OUT | NERROR_OUT | 0xFFFFEA4C | 0 | O | Hi-Z (Open Drain) | |
P9 | PMIC_CLKOUT | SOP[2] | 0xFFFFEA68 | During Power Up | I | Output Disabled | Pull Down |
GPIO_27 | 0 | IO | |||||
PMIC_CLKOUT | 1 | O | |||||
CHIRP_START | 6 | O | |||||
CHIRP_END | 7 | O | |||||
FRAME_START | 8 | O | |||||
EPWM1B | 11 | O | |||||
EPWM2A | 12 | O | |||||
R13 | QSPI[0] | GPIO_8 | 0xFFFFEA2C | 0 | IO | Output Disabled | Pull Down |
QSPI[0] | 1 | IO | |||||
SPIB_MISO | 2 | IO | |||||
N12 | QSPI[1] | GPIO_9 | 0xFFFFEA30 | 0 | IO | Output Disabled | Pull Down |
QSPI[1] | 1 | I | |||||
SPIB_MOSI | 2 | IO | |||||
SPIB_CS_N_2 | 8 | IO | |||||
R14 | QSPI[2] | GPIO_10 | 0xFFFFEA34 | 0 | IO | Output Disabled | Pull Down |
QSPI[2] | 1 | I | |||||
CAN1_FD_TX | 8 | O | |||||
P12 | QSPI[3] | GPIO_11 | 0xFFFFEA38 | 0 | IO | Output Disabled | Pull Down |
QSPI[3] | 1 | I | |||||
CAN1_FD_RX | 8 | I | |||||
R12 | QSPI_CLK | GPIO_7 | 0xFFFFEA3C | 0 | IO | Output Disabled | Pull Down |
QSPI_CLK | 1 | O | |||||
SPIB_CLK | 2 | IO | |||||
DSS_UART_TX | 6 | O | |||||
P11 | QSPI_CS_N | GPIO_6 | 0xFFFFEA40 | 0 | IO | Output Disabled | Pull Up |
QSPI_CS_N | 1 | O | |||||
SPIB_CS_N | 2 | IO | |||||
N4 | RS232_RX | GPIO_15 | 0xFFFFEA74 | 0 | IO | Input Enabled | Pull Up |
RS232_RX | 1 | I | |||||
MSS_UARTA_RX | 2 | I | |||||
BSS_UART_TX | 6 | IO | |||||
MSS_UARTB_RX | 7 | IO | |||||
CAN1_FD_RX | 8 | I | |||||
I2C_SCL | 9 | IO | |||||
EPWM2A | 10 | O | |||||
EPWM2B | 11 | O | |||||
EPWM3A | 12 | O | |||||
N5 | RS232_TX | GPIO_14 | 0xFFFFEA78 | 0 | IO | Output Enabled | |
RS232_TX | 1 | O | |||||
MSS_UARTA_TX | 5 | IO | |||||
MSS_UARTB_TX | 6 | IO | |||||
BSS_UART_TX | 7 | IO | |||||
CAN1_FD_TX | 10 | O | |||||
I2C_SDA | 11 | IO | |||||
EPWM1A | 12 | O | |||||
EPWM1B | 13 | O | |||||
NDMM_EN | 14 | I | |||||
EPWM2A | 15 | O | |||||
E13 | SPIA_CLK | GPIO_3 | 0xFFFFEA14 | 0 | IO | Output Disabled | Pull Up |
SPIA_CLK | 1 | IO | |||||
CAN2_FD_RX | 6 | I | |||||
DSS_UART_TX | 7 | O | |||||
E15 | SPIA_CS_N | GPIO_30 | 0xFFFFEA18 | 0 | IO | Output Disabled | Pull Up |
SPIA_CS_N | 1 | IO | |||||
CAN2_FD_TX | 6 | 0 | |||||
E14 | SPIA_MISO | GPIO_20 | 0xFFFFEA10 | 0 | IO | Output Disabled | Pull Up |
SPIA_MISO | 1 | IO | |||||
CAN1_FD_TX | 2 | O | |||||
D13 | SPIA_MOSI | GPIO_19 | 0xFFFFEA0C | 0 | IO | Output Disabled | Pull Up |
SPIA_MOSI | 1 | IO | |||||
CAN1_FD_RX | 2 | I | |||||
DSS_UART_TX | 8 | O | |||||
F14 | SPIB_CLK | GPIO_5 | 0xFFFFEA24 | 0 | IO | Output Disabled | Pull Up |
SPIB_CLK | 1 | IO | |||||
MSS_UARTA_RX | 2 | I | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | O | |||||
CAN1_FD_RX | 8 | I | |||||
H14 | SPIB_CS_N | GPIO_4 | 0xFFFFEA28 | 0 | IO | Output Disabled | Pull Up |
SPIB_CS_N | 1 | IO | |||||
MSS_UARTA_TX | 2 | O | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | IO | |||||
QSPI_CLK_EXT | 8 | I | |||||
CAN1_FD_TX | 9 | O | |||||
G14 | SPIB_MISO | GPIO_22 | 0xFFFFEA20 | 0 | IO | Output Disabled | Pull Up |
SPIB_MISO | 1 | IO | |||||
I2C_SCL | 2 | IO | |||||
DSS_UART_TX | 6 | O | |||||
F13 | SPIB_MOSI | GPIO_21 | 0xFFFFEA1C | 0 | IO | Output Disabled | Pull Up |
SPIB_MOSI | 1 | IO | |||||
I2C_SDA | 2 | IO | |||||
P13 | SPI_HOST_INTR | GPIO_12 | 0xFFFFEA00 | 0 | IO | Output Disabled | Pull Down |
SPI_HOST_INTR | 1 | O | |||||
SPIB_CS_N_1 | 6 | IO | |||||
P4 | SYNC_IN | GPIO_28 | 0xFFFFEA6C | 0 | IO | Output Disabled | Pull Down |
SYNC_IN | 1 | I | |||||
MSS_UARTB_RX | 6 | IO | |||||
DMM_MUX_IN | 7 | I | |||||
SYNC_OUT | 9 | O | |||||
G13 | SYNC_OUT | SOP[1] | 0xFFFFEA70 | During Power Up | I | Output Disabled | Pull Down |
GPIO_29 | 0 | IO | |||||
SYNC_OUT | 1 | O | |||||
DMM_MUX_IN | 9 | I | |||||
SPIB_CS_N_1 | 10 | IO | |||||
SPIB_CS_N_2 | 11 | IO | |||||
P10 | TCK | GPIO_17 | 0xFFFFEA50 | 0 | IO | Input Enabled | Pull Down |
TCK | 1 | I | |||||
MSS_UARTB_TX | 2 | O | |||||
CAN1_FD_TX | 8 | O | |||||
R11 | TDI | GPIO_23 | 0xFFFFEA58 | 0 | IO | Input Enabled | Pull Up |
TDI | 1 | I | |||||
MSS_UARTA_RX | 2 | I | |||||
N13 | TDO | SOP[0] | 0xFFFFEA5C | During Power Up | I | Output Enabled | |
GPIO_24 | 0 | IO | |||||
TDO | 1 | O | |||||
MSS_UARTA_TX | 2 | O | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | O | |||||
NDMM_EN | 9 | I | |||||
N10 | TMS | GPIO_18 | 0xFFFFEA54 | 0 | IO | Input Enabled | Pull Down |
TMS | 1 | I | |||||
BSS_UART_TX | 2 | O | |||||
CAN1_FD_RX | 6 | I | |||||
N9 | WARM_RESET | WARM_RESET | 0xFFFFEA48 | 0 | IO | Hi-Z Input (Open Drain) |
The following list describes the table column headers:
IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Default Pin/Ball Name | Package Ball /Pin (Address) | Pin Mux Config Register |
---|---|---|
SPI_HOST_INTR | P13 | 0xFFFFEA00 |
GPIO_0 | H13 | 0xFFFFEA04 |
GPIO_1 | J13 | 0xFFFFEA08 |
SPIA_MOSI | D13 | 0xFFFFEA0C |
SPIA_MISO | E14 | 0xFFFFEA10 |
SPIA_CLK | E13 | 0xFFFFEA14 |
SPIA_CS_N | E15 | 0xFFFFEA18 |
SPIB_MOSI | F13 | 0xFFFFEA1C |
SPIB_MISO | G14 | 0xFFFFEA20 |
SPIB_CLK | F14 | 0xFFFFEA24 |
SPIB_CS_N | H14 | 0xFFFFEA28 |
QSPI[0] | R13 | 0xFFFFEA2C |
QSPI[1] | N12 | 0xFFFFEA30 |
QSPI[2] | R14 | 0xFFFFEA34 |
QSPI[3] | P12 | 0xFFFFEA38 |
QSPI_CLK | R12 | 0xFFFFEA3C |
QSPI_CS_N | P11 | 0xFFFFEA40 |
NERROR_IN | N7 | 0xFFFFEA44 |
WARM_RESET | N9 | 0xFFFFEA48 |
NERROR_OUT | N6 | 0xFFFFEA4C |
TCK | P10 | 0xFFFFEA50 |
TMS | N10 | 0xFFFFEA54 |
TDI | R11 | 0xFFFFEA58 |
TDO | N13 | 0xFFFFEA5C |
MCU_CLKOUT | N8 | 0xFFFFEA60 |
GPIO_2 | K13 | 0xFFFFEA64 |
PMIC_CLKOUT | P9 | 0xFFFFEA68 |
SYNC_IN | P4 | 0xFFFFEA6C |
SYNC_OUT | G13 | 0xFFFFEA70 |
RS232_RX | N4 | 0xFFFFEA74 |
RS232_TX | N5 | 0xFFFFEA78 |
GPIO_31 | R4 | 0xFFFFEA7C |
GPIO_32 | P5 | 0xFFFFEA80 |
GPIO_33 | R5 | 0xFFFFEA84 |
GPIO_34 | P6 | 0xFFFFEA88 |
GPIO_35 | R7 | 0xFFFFEA8C |
GPIO_36 | P7 | 0xFFFFEA90 |
GPIO_37 | R8 | 0xFFFFEA94 |
GPIO_38 | P8 | 0xFFFFEA98 |
GPIO_47 | N15 | 0xFFFFEABC |
DMM_SYNC | N14 | 0xFFFFEAC0 |
The register layout is as follows:
BIT | FIELD | TYPE | RESET (POWER ON DEFAULT) | DESCRIPTION |
---|---|---|---|---|
31-11 | NU | RW | 0 | Reserved |
10 | SC | RW | 0 | IO
slew rate control: 0 = Higher slew rate 1 = Lower slew rate |
9 | PUPDSEL | RW | 0 | Pullup/PullDown Selection 0 = Pull Down 1 = Pull Up (This field is valid only if Pull Inhibit is set as '0') |
8 | PI | RW | 0 | Pull
Inhibit/Pull Disable 0 = Enable 1 = Disable |
7 | OE_OVERRIDE | RW | 1 | Output Override |
6 | OE_OVERRIDE_CTRL | RW | 1 | Output Override Control: (A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is associated with for example a SPI Chip select) |
5 | IE_OVERRIDE | RW | 0 | Input Override |
4 | IE_OVERRIDE_CTRL | RW | 0 | Input
Override Control: (A '1' here overrides any i/p value on this IO with a desired value) |
3-0 | FUNC_SEL | RW | 1 | Function select for Pin Multiplexing (Refer to the Pin Mux Sheet) |
PARAMETERS(1)(2) | MIN | MAX | UNIT | |
---|---|---|---|---|
VDDIN | 1.2 V digital power supply | –0.5 | 1.4 | V |
VIN_SRAM | 1.2 V power rail for internal SRAM | –0.5 | 1.4 | V |
VNWA | 1.2 V power rail for SRAM array back bias | –0.5 | 1.4 | V |
VIOIN | I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. | –0.5 | 3.8 | V |
VIOIN_18 | 1.8 V supply for CMOS IO | –0.5 | 2 | V |
VIN_18CLK | 1.8 V supply for clock module | –0.5 | 2 | V |
VIOIN_18DIFF | 1.8 V supply for LVDS port | –0.5 | 2 | V |
VIN_13RF1 | 1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could be shorted on the board. | –0.5 | 1.45 | V |
VIN_13RF2 | ||||
VIN_13RF1 (1-V Internal LDO bypass mode) |
Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. | –0.5 | 1.4 | V |
VIN_13RF2 (1-V Internal LDO bypass mode) |
||||
VIN_18BB | 1.8-V Analog baseband power supply | –0.5 | 2 | V |
VIN_18VCO supply | 1.8-V RF VCO supply | –0.5 | 2 | V |
RX1-4 | Externally applied power on RF inputs | 10 | dBm | |
TX1-3 | Externally applied power on RF outputs(3) | 10 | dBm | |
Input and output voltage range | Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State) | –0.3V | VIOIN + 0.3 | V |
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V (Transient Overshoot/Undershoot) or external oscillator input | VIOIN + 20% up to 20% of signal period | |||
CLKP, CLKM | Input ports for reference crystal | –0.5 | 2 | V |
Clamp current | Input or Output Voltages 0.3 V above or below their respective power rails. Limit clamp current that flows through the internal diode protection cells of the I/O. | –20 | 20 | mA |
TJ | Operating junction temperature range | –40 | 125 | °C |
TSTG | Storage temperature range after soldered onto PC board | –55 | 150 | °C |
JUNCTION TEMPERATURE (TJ)(1)(2) | OPERATING CONDITION | NOMINAL CVDD VOLTAGE (V) | POWER-ON HOURS [POH] (HOURS) |
---|---|---|---|
–40°C | 100% duty cycle | 1.2 | 600 (6%) |
75°C | 2000 (20%) | ||
95°C | 6500 (65%) | ||
125°C | 900 (9%) |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDIN | 1.2 V digital power supply | 1.14 | 1.2 | 1.32 | V |
VIN_SRAM | 1.2 V power rail for internal SRAM | 1.14 | 1.2 | 1.32 | V |
VNWA | 1.2 V power rail for SRAM array back bias | 1.14 | 1.2 | 1.32 | V |
VIOIN | I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. | 3.15 | 3.3 | 3.45 | V |
1.71 | 1.8 | 1.89 | |||
VIOIN_18 | 1.8 V supply for CMOS IO | 1.71 | 1.8 | 1.9 | V |
VIN_18CLK | 1.8 V supply for clock module | 1.71 | 1.8 | 1.9 | V |
VIOIN_18DIFF | 1.8 V supply for LVDS port | 1.71 | 1.8 | 1.9 | V |
VIN_13RF1 | 1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board | 1.23 | 1.3 | 1.36 | V |
VIN_13RF2 | |||||
VIN_13RF1 (1-V Internal LDO bypass mode) | Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. | 0.95 | 1 | 1.05 | V |
VIN_13RF2 (1-V Internal LDO bypass mode) | |||||
VIN18BB | 1.8-V Analog baseband power supply | 1.71 | 1.8 | 1.9 | V |
VIN_18VCO | 1.8V RF VCO supply | 1.71 | 1.8 | 1.9 | V |
VIH | Voltage Input High (1.8 V mode) | 1.17 | V | ||
Voltage Input High (3.3 V mode) | 2.25 | ||||
VIL | Voltage Input Low (1.8 V mode) | 0.3*VIOIN | V | ||
Voltage Input Low (3.3 V mode) | 0.62 | ||||
VOH | High-level output threshold (IOH = 6 mA) | VIOIN – 450 | mV | ||
VOL | Low-level output threshold (IOL = 6 mA) | 450 | mV | ||
NRESET SOP[2:0] | VIL (1.8V Mode) | 0.45 | V | ||
VIH (1.8V Mode) | 0.96 | ||||
VIL (3.3V Mode) | 0.65 | ||||
VIH (3.3V Mode) | 1.57 |
Table 7-1 describes the four rails from an external power supply block of the AWR6843 device.
SUPPLY | DEVICE BLOCKS POWERED FROM THE SUPPLY | RELEVANT IOS IN THE DEVICE |
---|---|---|
1.8 V | Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC, LVDS | Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF,
VIOIN_18 LDO Output: VOUT_14SYNTH, VOUT_14APLL |
1.3 V (or 1 V in internal LDO bypass mode)(1) | Power Amplifier, Low Noise Amplifier, Mixers and LO Distribution | Input: VIN_13RF2, VIN_13RF1 LDO Output: VOUT_PA |
3.3 V (or 1.8 V for 1.8 V I/O mode) | Digital I/Os | Input VIOIN |
1.2 V | Core Digital and SRAMs | Input: VDDIN, VIN_SRAM |
The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 7-2 are defined to meet a target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.
FREQUENCY (kHz) | RF RAIL | VCO/IF RAIL | |
---|---|---|---|
1.0 V (INTERNAL LDO BYPASS) (µVRMS) |
1.3 V (µVRMS) | 1.8 V (µVRMS) | |
137.5 | 7 | 648 | 83 |
275 | 5 | 76 | 21 |
550 | 3 | 22 | 11 |
1100 | 2 | 4 | 6 |
2200 | 11 | 82 | 13 |
4400 | 13 | 93 | 19 |
6600 | 22 | 117 | 29 |
Table 7-3 and Table 7-4 summarize the power consumption at the power terminals.
PARAMETER | SUPPLY NAME | DESCRIPTION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
Current consumption(1) | VDDIN, VIN_SRAM, VNWA | Total current drawn by all nodes driven by 1.2V rail | 1000 | mA | ||
VIN_13RF1, VIN_13RF2 | Total current drawn by all nodes driven by 1.3V or 1.0V rail (2TX, 4 RX simultaneously)(3) | 2000 | ||||
VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCO | Total current drawn by all nodes driven by 1.8V rail | 850 | ||||
VIOIN | Total current drawn by all nodes driven by 3.3V rail(2) | 50 |
PARAMETER | CONDITION | DESCRIPTION | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
Average power consumption(1) | 1.0-V internal LDO bypass mode | 24% duty cycle | 1TX, 4RX | Regular power ADC mode 6.4 Msps complex transceiver, 13.13-ms frame, 64 chirps, 256 samples/chirp, 8.5-µs interchirp time, DSP + Hardware accelerator active | 1.19 | W | ||
2TX, 4RX(1) | 1.25 | |||||||
48% duty cycle | 1TX, 4RX | Regular power ADC mode 6.4 Msps complex transceiver, 13.13-ms frame, 64 chirps, 256 samples/chirp, 8.5-µs interchirp time, DSP + Hardware accelerator active | 1.62 | |||||
2TX, 4RX(1) | 1.75 |
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
Receiver | Noise figure | 60 to 64 GHz | 12 | dB | ||
1-dB compression point (Out Of Band )(1) | –12 | dBm | ||||
Maximum gain | 48 | dB | ||||
Gain range | 18 | dB | ||||
Gain step size | 2 | dB | ||||
IF bandwidth(2) | 10 | MHz | ||||
ADC sampling rate (real) | 25 | Msps | ||||
ADC sampling rate (complex 1x) | 12.5 | Msps | ||||
ADC resolution | 12 | Bits | ||||
Idle Channel Spurs | –90 | dBFS | ||||
Transmitter | Output power | 12 | dBm | |||
Power backoff range | 26 | dB | ||||
Clock subsystem | Frequency range | 60 | 64 | GHz | ||
Ramp rate | 250 | MHz/µs | ||||
Phase noise at 1-MHz offset | 60 to 64 GHz | –93 | dBc/Hz |
Available HPF Corner Frequencies (kHz) | |
HPF1 | HPF2 |
175, 235, 350, 700 | 350, 700, 1400, 2800 |
Figure 7-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
DSP Subsystem (C674 Family) | Clock Speed | 600 | MHz | |||
L1 Code Memory | 32 | KB | ||||
L1 Data Memory | 32 | KB | ||||
L2 Memory | 256 | KB | ||||
Main Subsystem (R4F Family) | Clock Speed | 200 | MHz | |||
Tightly Coupled Memory - A (Program) | 512 | KB | ||||
Tightly Coupled Memory - B (Data) | 192 | KB | ||||
Shared Memory | Shared L3 Memory | 768 | KB |