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  • AWR6443、AWR6843 单芯片 60GHz 至 64GHz 毫米波传感器

    • ZHCSL77D April   2020  – January 2022 AWR6443 , AWR6843

      PRODUCTION DATA  

  • CONTENTS
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  • AWR6443、AWR6843 单芯片 60GHz 至 64GHz 毫米波传感器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
    1.     Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Power Supply Sequencing and Reset Timing
      2. 7.10.2  Input Clocks and Oscillators
        1. 7.10.2.1 Clock Specifications
      3. 7.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.3.1 Peripheral Description
        2. 7.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.3.2.1 SPI Timing Conditions
          2. 7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 7.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 7.10.3.3 SPI Peripheral Mode I/O Timings
          1. 7.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 7.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.10.4  LVDS Interface Configuration
        1. 7.10.4.1 LVDS Interface Timings
      5. 7.10.5  General-Purpose Input/Output
        1. 7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 7.10.7  Serial Communication Interface (SCI)
        1. 7.10.7.1 SCI Timing Requirements
      8. 7.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 7.10.8.1 I2C Timing Requirements
      9. 7.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 7.10.9.1 QSPI Timing Conditions
        2. 7.10.9.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.10.9.3 QSPI Switching Characteristics
      10. 7.10.10 ETM Trace Interface
        1. 7.10.10.1 ETMTRACE Timing Conditions
        2. 7.10.10.2 ETM TRACE Switching Characteristics
      11. 7.10.11 Data Modification Module (DMM)
        1. 7.10.11.1 DMM Timing Requirements
      12. 7.10.12 JTAG Interface
        1. 7.10.12.1 JTAG Timing Conditions
        2. 7.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interface
      4. 8.3.4 Host Interface
      5. 8.3.5 Main Subsystem Cortex-R4F
      6. 8.3.6 DSP Subsystem
      7. 8.3.7 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  9. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  11. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tray Information for ABL, 10.4 × 10.4 mm
  13. 重要声明
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DATA SHEET

AWR6443、AWR6843 单芯片 60GHz 至 64GHz 毫米波传感器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • FMCW 收发器
    • 集成 PLL、发送器、接收器、基带和 ADC
    • 60GHz 至 64GHz 的覆盖范围，具有 4GHz 的连续带宽
    • 四个接收通道
    • 三个发送通道
    • 支持 6 位移相器
    • 基于分数 N PLL 的超精确线性调频脉冲引擎
    • TX 功率：12dBm
    • RX 噪声系数：
      • 12dB
    • 1MHz 时的相位噪声：
      • –93dBc/Hz
  • 内置校准和自检
    • 基于 Arm®Cortex®-R4F 的无线电控制系统
    • 内置固件 (ROM)
    • 针对工艺和温度进行自校准的系统
    • 在符合功能安全标准的器件上提供嵌入式自监控，无需主机处理器参与
  • 用于高级信号处理的 C674x DSP（仅限 AWR6843）
  • 用于 FFT、滤波和 CFAR 处理的硬件加速器
  • 存储器压缩
  • 用于物体检测和接口控制的 Arm® Cortex®-R4F 微控制器
    • 支持自主模式（从 QSPI 闪存加载用户应用）
  • 具有 ECC 的内部存储器
    • AWR6843：1.75MB，分为 MSS 程序 RAM (512KB)、MSS 数据 RAM (192KB)、DSP L1RAM (64KB) 和 L2 RAM (256KB) 以及 L3 雷达数据立方体 RAM (768KB)
    • AWR6443：1.4MB，分为 MSS 程序 RAM (512KB)、MSS 数据 RAM (192KB) 和 L3 雷达数据立方体 RAM (768KB)
    • 技术参考手册包括允许的大小修改
  • 为用户应用提供的其他接口
    • 多达 6 个 ADC 通道（低采样率监控）
    • 多达 2 个 SPI 端口
    • 多达 2 个 UART
    • 2 个 CAN-FD 接口
    • I2C
    • GPIO
    • 用于原始 ADC 数据和调试仪表的双通道 LVDS 接口
  • 器件安全（在部分器件型号上）
    • 支持经过身份验证和加密的安全引导
    • 具有密钥撤销功能的客户可编程根密钥、对称密钥（256 位）、非对称密钥（最高 RSA-2K）
    • 加密软件加速器 – PKA、AES（最高 256 位）、SHA（最高 256 位）、TRNG/DRGB
  • 符合功能安全标准
    • 专为功能安全应用开发
    • 文档有助于使 ISO 26262 功能安全系统设计满足 ASIL-D 级要求
    • 硬件完整性高达 ASIL-B 级
    • 安全相关认证
      • 经 TUV SUD 进行 ISO 26262 认证达到 ASIL B 级
  • 也提供非功能安全型号
  • 符合 AEC-Q100 标准
  • 电源管理
    • 内置 LDO 网络，可增强 PSRR
    • I/O 支持双电压 3.3V/1.8V
  • 时钟源
    • 具有内部振荡器的 40.0MHz 晶体
    • 支持频率为 40MHz 的外部振荡器
    • 支持外部驱动、频率为 40MHz 的时钟（方波/正弦波）
  • 轻松的硬件设计
    • 0.65mm 间距、161 引脚 10.4mm × 10.4mm 覆晶 BGA 封装，可实现轻松组装和低成本 PCB 设计
    • 小解决方案尺寸
  • 运行条件：
    • 结温范围为 –40°C 至 125°C

2 应用

  • 车内感应
  • 车内儿童检测
  • 占位检测
  • 安全带提醒装置
  • 驾驶员生命体征监测
  • 脚踢传感器/接入传感器
  • 手势识别

3 说明

该 AWR 器件是一款能够在 60GHz 至 64GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感器。该器件采用 TI 的低功耗 45nm RFCMOS 工艺制造，并且在超小封装中实现了出色的集成度。这是适用于汽车领域低功耗、自监控、超精确雷达系统的理想解决方案。当前提供多种符合汽车标准的型号，包括功能安全合规型器件和非功能安全器件。

器件信息
器件型号 封装(1) 封装尺寸 托盘/卷带包装
AWR6843AQGABLRQ1 FCBGA (161) 10.4mm × 10.4mm 卷带包装
AWR6843AQGABLQ1 FCBGA (161) 10.4mm × 10.4mm 托盘
AWR6843ABGABLRQ1 FCBGA (161) 10.4mm × 10.4mm 卷带包装
AWR6843ABGABLQ1 FCBGA (161) 10.4mm × 10.4mm 托盘
AWR6843ABSABLRQ1 FCBGA (161) 10.4mm × 10.4mm 卷带包装
AWR6843ABSABLQ1 FCBGA (161) 10.4mm × 10.4mm 托盘
AWR6443ABGABLRQ1 FCBGA (161) 10.4mm × 10.4mm 卷带包装
AWR6443ABGABLQ1 FCBGA (161) 10.4mm × 10.4mm 托盘
(1) 如需更多信息，请参阅Section 12机械、封装和可订购信息。

4 功能方框图

图 4-1 展示了器件的功能方框图

GUID-99F09B03-02EB-4284-AB28-79EBE39E44C5-low.gif 图 4-1 功能方框图

Revision History

Changes from April 2, 2021 to January 10, 2022 (from Revision C (April 2021) to Revision D (January 2022))

  • 通篇：进行了更新，以反映功能安全合规性；在主/从术语方面改用了更具包容性的措辞Go
  • （特性）：更新了功能安全合规性认证资料；添加了关于器件安全的详细信息；提及了毫米波传感器的额定工作温度范围Go
  • （器件信息）：添加了功能安全合规型安全量产器件 AWR6843ABSABLRQ1 和 AWR6843ABSABLQ1Go
  • (Device Comparison) Changed/Updated to include AWR1843AOP; Updated/Changed the AWR6843AOP Product status from "AI" to "PD" Go
  • (Device Comparison) Removed information on Functional-Safety compliance from the table and instead added a table-note for this and LVDS Interface; Additional information on Device security updated.Go
  • (Signal Descriptions): Updated/Changed CLKP and CLKM descriptionsGo
  • (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and a table-note for the signal level applied on TX.Go
  • (Clock Specifications): Updated/Changed Crystal Electrical Characteristics (Oscillator Mode) to reflect correct device operating temperature range.Go
  • (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppmGo
  • (QSPI Timings):Updated/Changed Setup Time from 7.3us to 5us and Hold Time from 1.5us to 1us for QSPI TimingsGo
  • (QSPI Timings): Updated/Changed Delay time, sclk falling edge to d[1] transition [Q6, Q9] from -3.5us to -2.5us (Min) and 7us to 4us (Max) in QSPI Switching CharacteristicsGo
  • (Transmit Subsystem): Updated/Changed figure.Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go
  • (Device Nomenclature) : Updated/modified figure to reflect Functional Safety complianceGo
  • Tray Information for ABL, 10.4 × 10.4 mm: Added tray information for secure part.Go

5 Device Comparison

Unless otherwise noted, the device-specific information, in this document, relates to both the AWR6843 and AWR6443 devices. The device differences are highlighted in Table 5-1, Device Features Comparison.

Table 5-1 Device Features Comparison
FUNCTION AWR6843AOP AWR1843AOP AWR6843(1) AWR6443(1) AWR1843 AWR1642 AWR1443
Antenna on Package (AOP) Yes Yes — — — — —
Number of receivers 4 4 4 4 4 4 4
Number of transmitters 3(2) 3(2) 3(2) 3(2) 3(2) 2 3
RF frequency range 60 to 64 GHz 76 to 81 GHz 60 to 64 GHz 60 to 64 GHz 76 to 81 GHz 76 to 81 GHz 76 to 81 GHz
On-chip memory 1.75MB 2MB 1.75MB 1.4MB 2MB 1.5MB 576KB
Max I/F (Intermediate Frequency) (MHz) 10 10 10 10 10 5 5
Max real sampling rate (Msps) 25 25 25 25 25 12.5 12.5
Max complex sampling rate (Msps) 12.5 12.5 12.5 12.5 12.5 6.25 6.25
Device Security(3) Yes Yes Yes — Yes Yes —
Processors
MCU (R4F) Yes Yes Yes Yes Yes Yes Yes
DSP (C674x) Yes Yes Yes — Yes Yes —
Peripherals
Serial Peripheral Interface (SPI) ports 2 2 2 2 2 2 1
Quad Serial Peripheral Interface (QSPI) Yes Yes Yes Yes Yes Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1 1 1 1 1 1
Controller Area Network (DCAN) interface — 1 — — 1 1 1
Controller Area Network (CAN-FD) interface 2 1 2 2 1 — —
Trace Yes Yes Yes Yes Yes Yes —
PWM Yes Yes Yes Yes Yes Yes —
Hardware In Loop (HIL/DMM) Yes Yes Yes Yes Yes Yes —
GPADC Yes Yes Yes Yes Yes Yes Yes
LVDS/Debug(4) Yes Yes Yes Yes Yes Yes Yes
CSI2 — — — — — — —
Hardware accelerator Yes Yes Yes Yes Yes — Yes
1-V bypass mode Yes Yes Yes Yes Yes Yes Yes
JTAG Yes Yes Yes Yes Yes Yes Yes
Product status Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD(5) PD(5) PD(5) PD(5) PD(5) PD(5) PD(5)
(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation for more details. Non-Functional Safety Variants are also available for AWR6843 device.
(2) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT PA pin.
(3) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part variants as indicated by the Device Type identifier in Section 3, Device Information table.
(4) The LVDS interface is not a production interface and is only used for debug.
(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. ADVANCE INFORMATION for pre-production products; subject to change without notice.

5.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

    mmWave sensorsTI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less power using the smallest footprint mmWave sensor portfolio for automotive applications.
    Automotive mmWave sensorsTI’s automotive mmWave sensor portfolio offers high-performance radar front end to ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable sensor portfolio enables design and development of ADAS system solution for every performance, application and sensor configuration ranging from comfort functions to safety functions in all vehicles.
    Companion products for AWR6843Review products that are frequently purchased or used in conjunction with this product.
    Reference designs for AWR6843TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.
    Vehicle occupant detection reference design This reference design demonstrates the use of the AWR6843 60GHz single-chip mmWave sensor with integrated DSP, as a Vehicle Occupant Detection (VOD) and Child Presence Detection (CPD) Sensor enabling the detection of life forms in a vehicle. This design provides a reference software processing chain which runs on the C674x DSP, enabling the generation of a heat map to detect occupants in a Field of View (FOV) of ±60 degrees.

6 Terminal Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows the pin locations for the 161-pin FCBGA package. Figure 6-2, Figure 6-3, Figure 6-4, and Figure 6-5 show the same pins, but split into four quadrants.

GUID-E5AFC274-748E-4EF2-BC74-EAB9A406A7E6-low.gif Figure 6-1 Pin Diagram (Top View)
GUID-95F2344A-66AF-44E6-86D8-F75EBF238280-low.gif Figure 6-2 Top Left Quadrant
GUID-B6148122-9A67-462E-B046-CC06F81533D3-low.gif Figure 6-3 Top Right Quadrant
GUID-8802BF39-AE4F-4312-9EE6-8A997687F569-low.gif Figure 6-4 Bottom Left Quadrant
GUID-27AA4396-20D3-4117-A350-C24268C5809B-low.gif Figure 6-5 Bottom Right Quadrant

6.2 Signal Descriptions

Note:

All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.

Note:

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.

6.2.1 Signal Descriptions - Digital

SIGNAL NAMEPIN TYPEDESCRIPTIONBALL NO.
BSS_UART_TXODebug UART Transmit [Radar Block]F14, H14, K13, N10, N13, N4, N5, R8
CAN1_FD_RXICAN1 FD (MCAN) Receive SignalD13, F14, N10, N4, P12
CAN1_FD_TXOCAN1 FD (MCAN) Transmit SignalE14, H14, N5, P10, R14
CAN2_FD_RXICAN2 FD (MCAN) Receive SignalE13
CAN2_FD_TXIOCAN2 FD (MCAN) Transmit SignalE15
DMM0IDebug Interface (Hardware In Loop) - Data LineR4
DMM1IDebug Interface (Hardware In Loop) - Data LineP5
DMM2IDebug Interface (Hardware In Loop) - Data LineR5
DMM3IDebug Interface (Hardware In Loop) - Data LineP6
DMM4IDebug Interface (Hardware In Loop) - Data LineR7
DMM5IDebug Interface (Hardware In Loop) - Data LineP7
DMM6IDebug Interface (Hardware In Loop) - Data LineR8
DMM7IDebug Interface (Hardware In Loop) - Data LineP8
DMM_CLKIDebug Interface (Hardware In Loop) - ClockN15
DMM_MUX_INIDebug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances)G13, J13, P4
DMM_SYNCIDebug Interface (Hardware In Loop) - SyncN14
DSS_UART_TXODebug UART Transmit [DSP]D13, E13, G14, P8, R12
EPWM1AOPWM Module 1 - Output AN5, N8
EPWM1BOPWM Module 1 - Output BH13, N5, P9
EPWM1SYNCIIJ13
EPWM2AOPWM Module 2- Output AH13, N4, N5, P9
EPWM2BOPWM Module 2 - Output BN4
EPWM2SYNCOOR7
EPWM3AOPWM Module 3 - Output AN4
EPWM3SYNCOOP6
GPIO_0IOGeneral-purpose I/OH13
GPIO_1IOGeneral-purpose I/OJ13
GPIO_2IOGeneral-purpose I/OK13
GPIO_3IOGeneral-purpose I/OE13
GPIO_4IOGeneral-purpose I/OH14
GPIO_5IOGeneral-purpose I/OF14
GPIO_6IOGeneral-purpose I/OP11
GPIO_7IOGeneral-purpose I/OR12
GPIO_8IOGeneral-purpose I/OR13
GPIO_9IOGeneral-purpose I/ON12
GPIO_10IOGeneral-purpose I/OR14
GPIO_11IOGeneral-purpose I/OP12
GPIO_12IOGeneral-purpose I/OP13
GPIO_13IOGeneral-purpose I/OH13
GPIO_14IOGeneral-purpose I/ON5
GPIO_15IOGeneral-purpose I/ON4
GPIO_16IOGeneral-purpose I/OJ13
GPIO_17IOGeneral-purpose I/OP10
GPIO_18IOGeneral-purpose I/ON10
GPIO_19IOGeneral-purpose I/OD13
GPIO_20IOGeneral-purpose I/OE14
GPIO_21IOGeneral-purpose I/OF13
GPIO_22IOGeneral-purpose I/OG14
GPIO_23IOGeneral-purpose I/OR11
GPIO_24IOGeneral-purpose I/ON13
GPIO_25IOGeneral-purpose I/ON8
GPIO_26IOGeneral-purpose I/OK13
GPIO_27IOGeneral-purpose I/OP9
GPIO_28IOGeneral-purpose I/OP4
GPIO_29IOGeneral-purpose I/OG13
GPIO_30IOGeneral-purpose I/OC13
GPIO_31IOGeneral-purpose I/OR4
GPIO_32IOGeneral-purpose I/OP5
GPIO_33IOGeneral-purpose I/OR5
GPIO_34IOGeneral-purpose I/OP6
GPIO_35IOGeneral-purpose I/OR7
GPIO_36IOGeneral-purpose I/OP7
GPIO_37IOGeneral-purpose I/OR8
GPIO_38IOGeneral-purpose I/OP8
GPIO_47IOGeneral-purpose I/ON15
I2C_SCLIOI2C ClockG14, N4
I2C_SDAIOI2C DataF13, N5
LVDS_TXP[0]ODifferential data Out – Lane 0J14
LVDS_TXM[0]OJ15
LVDS_TXP[1]ODifferential data Out – Lane 1K14
LVDS_TXM[1]OK15
LVDS_CLKPODifferential clock OutL14
LVDS_CLKMOL15
LVDS_FRCLKPODifferential Frame ClockM14
LVDS_FRCLKMOM15
MCU_CLKOUTOProgrammable clock given out to external MCU or the processorN8
MSS_UARTA_RXIMain Subsystem - UART A ReceiveF14, N4, R11
MSS_UARTA_TXOMain Subsystem - UART A TransmitH14, N13, N5, R4
MSS_UARTB_RXIOMain Subsystem - UART B ReceiveN4, P4
MSS_UARTB_TXOMain Subsystem - UART B TransmitF14, H14, K13, N13, N5, P10, P7
NDMM_ENIDebug Interface (Hardware In Loop) Enable - Active Low SignalN13, N5
NERROR_INIFailsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by FirmwareN7
NERROR_OUTOOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.N6
PMIC_CLKOUTOOutput Clock from AWR6843 device for PMICH13, K13, P9
QSPI[0]IOQSPI Data Line #0 (Used with Serial Data Flash)R13
QSPI[1]IQSPI Data Line #1 (Used with Serial Data Flash)N12
QSPI[2]IQSPI Data Line #2 (Used with Serial Data Flash)R14
QSPI[3]IQSPI Data Line #3 (Used with Serial Data Flash)P12
QSPI_CLKOQSPI Clock (Used with Serial Data Flash)R12
QSPI_CLK_EXTIQSPI Clock (Used with Serial Data Flash)H14
QSPI_CS_NOQSPI Chip Select (Used with Serial Data Flash)P11
RS232_RXIDebug UART (Operates as Bus Master) - Receive SignalN4
RS232_TXODebug UART (Operates as Bus Master) - Transmit SignalN5
SOP[0]ISense On Power - Line#0N13
SOP[1]ISense On Power - Line#1G13
SOP[2]ISense On Power - Line#2P9
SPIA_CLKIOSPI Channel A - ClockE13
SPIA_CS_NIOSPI Channel A - Chip SelectE15
SPIA_MISOIOSPI Channel A - Master In Slave OutE14
SPIA_MOSIIOSPI Channel A - Master Out Slave InD13
SPIB_CLKIOSPI Channel B - ClockF14, R12
SPIB_CS_NIOSPI Channel B Chip Select (Instance ID 0)H14, P11
SPIB_CS_N_1IOSPI Channel B Chip Select (Instance ID 1)G13, J13, P13
SPIB_CS_N_2IOSPI Channel B Chip Select (Instance ID 2)G13, J13, N12
SPIB_MISOIOSPI Channel B - Master In Slave OutG14, R13
SPIB_MOSIIOSPI Channel B - Master Out Slave InF13, N12
SPI_HOST_INTROOut of Band Interrupt to an external host communicating over SPIP13
SYNC_INILow frequency Synchronization signal inputP4
SYNC_OUTOLow Frequency Synchronization Signal outputG13, J13, K13, P4
TCKIJTAG Test ClockP10
TDIIJTAG Test Data InputR11
TDOOJTAG Test Data OutputN13
TMSIJTAG Test Mode SignalN10
TRACE_CLKODebug Trace Output - ClockN15
TRACE_CTLODebug Trace Output - ControlN14
TRACE_DATA_0ODebug Trace Output - Data LineR4
TRACE_DATA_1ODebug Trace Output - Data LineP5
TRACE_DATA_2ODebug Trace Output - Data LineR5
TRACE_DATA_3ODebug Trace Output - Data LineP6
TRACE_DATA_4ODebug Trace Output - Data LineR7
TRACE_DATA_5ODebug Trace Output - Data LineP7
TRACE_DATA_6ODebug Trace Output - Data LineR8
TRACE_DATA_7ODebug Trace Output - Data LineP8
FRAME_STARTOPulse signal indicating the start of each frameN8, K13, P9
CHIRP_STARTOPulse signal indicating the start of each chirpN8, K13, P9
CHIRP_ENDOPulse signal indicating the end of each chirpN8, K13, P9
WARM_RESETIOOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.N9

6.2.2 Signal Descriptions - Analog

INTERFACESIGNAL NAMEPIN TYPEDESCRIPTIONBALL NO.
TransmittersTX1OSingle ended transmitter1 o/pB4
TX2OSingle ended transmitter2 o/pB6
TX3OSingle ended transmitter3 o/pB8
ReceiversRX1ISingle ended receiver1 i/pM2
RX2ISingle ended receiver2 i/pK2
RX3ISingle ended receiver3 i/pH2
RX4ISingle ended receiver4 i/pF2
ResetNRESETIPower on reset for chip. Active lowR3
Reference OscillatorCLKPIIn XTAL mode: Input for the reference crystal
In External clock mode: Single ended input reference clock port		B15
CLKMIIn XTAL mode: Feedback drive for the reference crystal
In External clock mode: Connect this port to ground		C15
Reference clockOSC_CLKOUTOReference clock output from clocking subsystem after cleanup PLL (1.4V output voltage swing).A14
Bandgap voltageVBGAPODevice's Band Gap Reference OutputB10
Power supplyVDDINPower1.2V digital power supplyH15, N11, P15, R6
VIN_SRAMPower1.2V power rail for internal SRAMG15
VNWAPower1.2V power rail for SRAM array back biasP14
VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supplyR10, F15
VIOIN_18Power1.8V supply for CMOS IOR9
VIN_18CLKPower1.8V supply for clock moduleB11
VIOIN_18DIFFPower1.8V supply for LVDS portD15
VPPPowerVoltage supply for fuse chainL13
Power supplyVIN_13RF1Power1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the boardG5, H5, J5
VIN_13RF2Power1.3V Analog and RF supplyC2,D2
VIN_18BBPower1.8V Analog base band power supplyK5, F5
VIN_18VCOPower1.8V RF VCO supplyB12
VSSGroundDigital groundL5, L6, L8, L10, K7, K8, K9, K10, K11, J6, J7, J8, J10, H7, H9, H11, G6, G7, G8, G10, F9, F11, E5, E6, E8, E10, E11, R15
VSSAGroundAnalog groundA1, A3, A5, A7, A9, A13, A15, B1, B3, B5, B7, B9, B14, C1, C3, C4, C5, C6, C7, C8, C9, C14, E1, E2, E3, F3, G1, G2, G3, H3, J1, J2, J3, K3, L1, L2, L3, M3, N1, N2, N3, R1
Internal LDO output/inputsVOUT_14APLLOInternal LDO outputA10
VOUT_14SYNTHOInternal LDO outputB13
VOUT_PAIOInternal LDO outputA2, B2
Test and Debug output for pre-production phase. Can be pinned out on production hardware for field debugAnalog Test1 / GPADC1IOAnalog IO dedicated for ADC serviceP1
Analog Test2 / GPADC2IOAnalog IO dedicated for ADC serviceP2
Analog Test3 / GPADC3IOAnalog IO dedicated for ADC serviceP3
Analog Test4 / GPADC4IOAnalog IO dedicated for ADC serviceR2
ANAMUX / GPADC5IOAnalog IO dedicated for ADC serviceC13
VSENSE / GPADC6IOAnalog IO dedicated for ADC serviceD14

6.3 Pin Attributes

Table 6-1 Pin Attributes (ABL0161 Package)
BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5][9] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8]
H13 GPIO_0 GPIO_13 0xFFFFEA04 0 IO Output Disabled Pull Down
GPIO_0 1 IO
PMIC_CLKOUT 2 O
EPWM1B 10 O
ePWM2A 11 O
J13 GPIO_1 GPIO_16 0xFFFFEA08 0 IO Output Disabled Pull Down
GPIO_1 1 IO
SYNC_OUT 2 O
DMM_MUX_IN 12 I
SPIB_CS_N_1 13 IO
SPIB_CS_N_2 14 IO
EPWM1SYNCI 15 I
K13 GPIO_2 GPIO_26 0xFFFFEA64 0 IO Output Disabled Pull Down
GPIO_2 1 IO
OSC_CLKOUT 2 O
MSS_UARTB_TX 7 O
BSS_UART_TX 8 O
SYNC_OUT 9 O
PMIC_CLKOUT 10 O
CHIRP_START 11 O
CHIRP_END 12 O
FRAME_START 13 O
R4 GPIO_31 TRACE_DATA_0 0xFFFFEA7C 0 O Output Disabled Pull Down
GPIO_31 1 IO
DMM0 2 I
MSS_UARTA_TX 4 IO
P5 GPIO_32 TRACE_DATA_1 0xFFFFEA80 0 O Output Disabled Pull Down
GPIO_32 1 IO
DMM1 2 I
R5 GPIO_33 TRACE_DATA_2 0xFFFFEA84 0 O Output Disabled Pull Down
GPIO_33 1 IO
DMM2 2 I
P6 GPIO_34 TRACE_DATA_3 0xFFFFEA88 0 O Output Disabled Pull Down
GPIO_34 1 IO
DMM3 2 I
EPWM3SYNCO 4 O
R7 GPIO_35 TRACE_DATA_4 0xFFFFEA8C 0 O Output Disabled Pull Down
GPIO_35 1 IO
DMM4 2 I
EPWM2SYNCO 4 O
P7 GPIO_36 TRACE_DATA_5 0xFFFFEA90 0 O Output Disabled Pull Down
GPIO_36 1 IO
DMM5 2 I
MSS_UARTB_TX 5 O
R8 GPIO_37 TRACE_DATA_6 0xFFFFEA94 0 O Output Disabled Pull Down
GPIO_37 1 IO
DMM6 2 I
BSS_UART_TX 5 O
P8 GPIO_38 TRACE_DATA_7 0xFFFFEA98 0 O Output Disabled Pull Down
GPIO_38 1 IO
DMM7 2 I
DSS_UART_TX 5 O
N15 GPIO_47 TRACE_CLK 0xFFFFEABC 0 O Output Disabled Pull Down
GPIO_47 1 IO
DMM_CLK 2 I
N14 DMM_SYNC TRACE_CTL 0xFFFFEAC0 0 O Output Disabled Pull Down
DMM_SYNC 2 I
N8 MCU_CLKOUT GPIO_25 0xFFFFEA60 0 IO Output Disabled Pull Down
MCU_CLKOUT 1 O
CHIRP_START 2 O
CHIRP_END 6 O
FRAME_START 7 O
EPWM1A 12 O
N7 NERROR_IN NERROR_IN 0xFFFFEA44 0 I Input
N6 NERROR_OUT NERROR_OUT 0xFFFFEA4C 0 O Hi-Z (Open Drain)
P9 PMIC_CLKOUT SOP[2] 0xFFFFEA68 During Power Up I Output Disabled Pull Down
GPIO_27 0 IO
PMIC_CLKOUT 1 O
CHIRP_START 6 O
CHIRP_END 7 O
FRAME_START 8 O
EPWM1B 11 O
EPWM2A 12 O
R13 QSPI[0] GPIO_8 0xFFFFEA2C 0 IO Output Disabled Pull Down
QSPI[0] 1 IO
SPIB_MISO 2 IO
N12 QSPI[1] GPIO_9 0xFFFFEA30 0 IO Output Disabled Pull Down
QSPI[1] 1 I
SPIB_MOSI 2 IO
SPIB_CS_N_2 8 IO
R14 QSPI[2] GPIO_10 0xFFFFEA34 0 IO Output Disabled Pull Down
QSPI[2] 1 I
CAN1_FD_TX 8 O
P12 QSPI[3] GPIO_11 0xFFFFEA38 0 IO Output Disabled Pull Down
QSPI[3] 1 I
CAN1_FD_RX 8 I
R12 QSPI_CLK GPIO_7 0xFFFFEA3C 0 IO Output Disabled Pull Down
QSPI_CLK 1 O
SPIB_CLK 2 IO
DSS_UART_TX 6 O
P11 QSPI_CS_N GPIO_6 0xFFFFEA40 0 IO Output Disabled Pull Up
QSPI_CS_N 1 O
SPIB_CS_N 2 IO
N4 RS232_RX GPIO_15 0xFFFFEA74 0 IO Input Enabled Pull Up
RS232_RX 1 I
MSS_UARTA_RX 2 I
BSS_UART_TX 6 IO
MSS_UARTB_RX 7 IO
CAN1_FD_RX 8 I
I2C_SCL 9 IO
EPWM2A 10 O
EPWM2B 11 O
EPWM3A 12 O
N5 RS232_TX GPIO_14 0xFFFFEA78 0 IO Output Enabled
RS232_TX 1 O
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
BSS_UART_TX 7 IO
CAN1_FD_TX 10 O
I2C_SDA 11 IO
EPWM1A 12 O
EPWM1B 13 O
NDMM_EN 14 I
EPWM2A 15 O
E13 SPIA_CLK GPIO_3 0xFFFFEA14 0 IO Output Disabled Pull Up
SPIA_CLK 1 IO
CAN2_FD_RX 6 I
DSS_UART_TX 7 O
E15 SPIA_CS_N GPIO_30 0xFFFFEA18 0 IO Output Disabled Pull Up
SPIA_CS_N 1 IO
CAN2_FD_TX 6 0
E14 SPIA_MISO GPIO_20 0xFFFFEA10 0 IO Output Disabled Pull Up
SPIA_MISO 1 IO
CAN1_FD_TX 2 O
D13 SPIA_MOSI GPIO_19 0xFFFFEA0C 0 IO Output Disabled Pull Up
SPIA_MOSI 1 IO
CAN1_FD_RX 2 I
DSS_UART_TX 8 O
F14 SPIB_CLK GPIO_5 0xFFFFEA24 0 IO Output Disabled Pull Up
SPIB_CLK 1 IO
MSS_UARTA_RX 2 I
MSS_UARTB_TX 6 O
BSS_UART_TX 7 O
CAN1_FD_RX 8 I
H14 SPIB_CS_N GPIO_4 0xFFFFEA28 0 IO Output Disabled Pull Up
SPIB_CS_N 1 IO
MSS_UARTA_TX 2 O
MSS_UARTB_TX 6 O
BSS_UART_TX 7 IO
QSPI_CLK_EXT 8 I
CAN1_FD_TX 9 O
G14 SPIB_MISO GPIO_22 0xFFFFEA20 0 IO Output Disabled Pull Up
SPIB_MISO 1 IO
I2C_SCL 2 IO
DSS_UART_TX 6 O
F13 SPIB_MOSI GPIO_21 0xFFFFEA1C 0 IO Output Disabled Pull Up
SPIB_MOSI 1 IO
I2C_SDA 2 IO
P13 SPI_HOST_INTR GPIO_12 0xFFFFEA00 0 IO Output Disabled Pull Down
SPI_HOST_INTR 1 O
SPIB_CS_N_1 6 IO
P4 SYNC_IN GPIO_28 0xFFFFEA6C 0 IO Output Disabled Pull Down
SYNC_IN 1 I
MSS_UARTB_RX 6 IO
DMM_MUX_IN 7 I
SYNC_OUT 9 O
G13 SYNC_OUT SOP[1] 0xFFFFEA70 During Power Up I Output Disabled Pull Down
GPIO_29 0 IO
SYNC_OUT 1 O
DMM_MUX_IN 9 I
SPIB_CS_N_1 10 IO
SPIB_CS_N_2 11 IO
P10 TCK GPIO_17 0xFFFFEA50 0 IO Input Enabled Pull Down
TCK 1 I
MSS_UARTB_TX 2 O
CAN1_FD_TX 8 O
R11 TDI GPIO_23 0xFFFFEA58 0 IO Input Enabled Pull Up
TDI 1 I
MSS_UARTA_RX 2 I
N13 TDO SOP[0] 0xFFFFEA5C During Power Up I Output Enabled
GPIO_24 0 IO
TDO 1 O
MSS_UARTA_TX 2 O
MSS_UARTB_TX 6 O
BSS_UART_TX 7 O
NDMM_EN 9 I
N10 TMS GPIO_18 0xFFFFEA54 0 IO Input Enabled Pull Down
TMS 1 I
BSS_UART_TX 2 O
CAN1_FD_RX 6 I
N9 WARM_RESET WARM_RESET 0xFFFFEA48 0 IO Hi-Z Input (Open Drain)

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 1).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 1).
  4. PINCNTL ADDRESS: MSS Address for PinMux Control
  5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
  7. BALL RESET STATE: The state of the terminal after supplies are stable after power-on-reset (NRESET) is asserted
  8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • Pull Up: Internal pullup
    • Pull Down: Internal pulldown
    • An empty box means No pull.
  9. Pin Mux Control Value maps to lower 4 bits of register.

IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:

Table 6-2 PAD IO Control Registers
Default Pin/Ball Name Package Ball /Pin (Address) Pin Mux Config Register
SPI_HOST_INTR P13 0xFFFFEA00
GPIO_0 H13 0xFFFFEA04
GPIO_1 J13 0xFFFFEA08
SPIA_MOSI D13 0xFFFFEA0C
SPIA_MISO E14 0xFFFFEA10
SPIA_CLK E13 0xFFFFEA14
SPIA_CS_N E15 0xFFFFEA18
SPIB_MOSI F13 0xFFFFEA1C
SPIB_MISO G14 0xFFFFEA20
SPIB_CLK F14 0xFFFFEA24
SPIB_CS_N H14 0xFFFFEA28
QSPI[0] R13 0xFFFFEA2C
QSPI[1] N12 0xFFFFEA30
QSPI[2] R14 0xFFFFEA34
QSPI[3] P12 0xFFFFEA38
QSPI_CLK R12 0xFFFFEA3C
QSPI_CS_N P11 0xFFFFEA40
NERROR_IN N7 0xFFFFEA44
WARM_RESET N9 0xFFFFEA48
NERROR_OUT N6 0xFFFFEA4C
TCK P10 0xFFFFEA50
TMS N10 0xFFFFEA54
TDI R11 0xFFFFEA58
TDO N13 0xFFFFEA5C
MCU_CLKOUT N8 0xFFFFEA60
GPIO_2 K13 0xFFFFEA64
PMIC_CLKOUT P9 0xFFFFEA68
SYNC_IN P4 0xFFFFEA6C
SYNC_OUT G13 0xFFFFEA70
RS232_RX N4 0xFFFFEA74
RS232_TX N5 0xFFFFEA78
GPIO_31 R4 0xFFFFEA7C
GPIO_32 P5 0xFFFFEA80
GPIO_33 R5 0xFFFFEA84
GPIO_34 P6 0xFFFFEA88
GPIO_35 R7 0xFFFFEA8C
GPIO_36 P7 0xFFFFEA90
GPIO_37 R8 0xFFFFEA94
GPIO_38 P8 0xFFFFEA98
GPIO_47 N15 0xFFFFEABC
DMM_SYNC N14 0xFFFFEAC0

The register layout is as follows:

Table 6-3 PAD IO Register Bit Descriptions
BIT FIELD TYPE RESET (POWER ON DEFAULT) DESCRIPTION
31-11 NU RW 0 Reserved
10 SC RW 0 IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
9 PUPDSEL RW 0 Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8 PI RW 0 Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7 OE_OVERRIDE RW 1 Output Override
6 OE_OVERRIDE_CTRL RW 1 Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is associated with for example a SPI Chip select)
5 IE_OVERRIDE RW 0 Input Override
4 IE_OVERRIDE_CTRL RW 0 Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
3-0 FUNC_SEL RW 1 Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)

7 Specifications

7.1 Absolute Maximum Ratings

PARAMETERS(1)(2)MINMAXUNIT
VDDIN1.2 V digital power supply–0.51.4V
VIN_SRAM1.2 V power rail for internal SRAM–0.51.4V
VNWA1.2 V power rail for SRAM array back bias–0.51.4V
VIOINI/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply.–0.53.8V
VIOIN_181.8 V supply for CMOS IO–0.52V
VIN_18CLK1.8 V supply for clock module–0.52V
VIOIN_18DIFF 1.8 V supply for LVDS port –0.5 2 V
VIN_13RF11.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could be shorted on the board.–0.51.45V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO bypass mode)		 Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. –0.5 1.4 V
VIN_13RF2
(1-V Internal LDO bypass mode)
VIN_18BB1.8-V Analog baseband power supply–0.52V
VIN_18VCO supply1.8-V RF VCO supply–0.52V
RX1-4 Externally applied power on RF inputs 10 dBm
TX1-3 Externally applied power on RF outputs(3) 10 dBm
Input and output voltage rangeDual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)–0.3VVIOIN + 0.3V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input		VIOIN + 20% up to
20% of signal period
CLKP, CLKMInput ports for reference crystal –0.52V
Clamp currentInput or Output Voltages 0.3 V above or below their respective power rails. Limit clamp current that flows through the internal diode protection cells of the I/O.–2020mA
TJ Operating junction temperature range –40 125 °C
TSTGStorage temperature range after soldered onto PC board–55150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on the TX output.

 
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