The ADC12D1620 offers a serial interface that allows access to the sixteen control registers within the device. The serial interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in their system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 7-10. See Figure 6-9 for the timing diagram and Timing Requirements: Serial Port Interface for timing specification details. Control register contents are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI, and, SCS pins may be left floating because they each have an internal pullup.

SCS: Each assertion (logic-low) of this signal starts a new register access, that is, the SDI command field must be ready on the following SCLK rising edge. The user is required to de-assert this signal after the 24th clock. If the SCS is de-asserted before the 24th clock, no data read/write occurs. For a read operation, if the SCS is asserted longer than 24 clocks, the SDO output holds the D0 bit until SCS is de-asserted. For a write operation, if the SCS is asserted longer than 24 clocks, data write occurs normally through the SDI input upon the 24th clock. Setup and hold times, t_SCS and t_HCS, with respect to the SCLK must be observed. SCS must be toggled in between register access cycles.

SCLK: This signal is used to register the input data (SDI) on the rising edge and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see f_SCLK in Timing Requirements: Serial Port Interface for more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a data field. If the SDI and SDO wires are shared (3-wire mode), during read operations it is necessary to tri-state the primary must be tristate while the data field is output by the ADC on SDO. The primary must be tri-state before the falling edge of the 8^th clock. If SDI and SDO are not shared (4-wire mode), then this is not necessary. Setup and hold times, t_SH and t_SSU, with respect to the SCLK must be observed.

SDO: This output is normally tri-state and is driven only when SCS is asserted, the first 8 bits of command data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the falling edge of the 8th clock. At the end of the access, when SCS is de-asserted, this output is tri-state once again. If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there is a bus turnaround time, t_BSU, from when the last bit of the command field was read in until the first bit of the data field is written out.

Table 7-11 shows the serial interface bit definitions.

The serial data protocol is shown for a read and write operation in Figure 7-3 and Figure 7-4, respectively.

Figure 7-3 Serial Data Protocol - Read Operation

Figure 7-4 Serial Data Protocol - Write Operation