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  • MSP430FR231x 混合信号微控制器

    • ZHCSF32E February   2016  – December 2019 MSP430FR2310 , MSP430FR2311

      PRODUCTION DATA.  

  • CONTENTS
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  • MSP430FR231x 混合信号微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Production Distribution of LPM Supply Currents
    10. 5.10 Typical Characteristics – Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 5-5 DCO FLL
        4. Table 5-6 DCO Frequency
        5. Table 5-7 REFO
        6. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 5-9 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.12.6  Timer_B
        1. Table 5-13 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-19 eUSCI (I2C Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-23 eCOMP0
      10. 5.12.10 Smart Analog Combo (SAC)
        1. Table 5-24 SAC0 (SAC-L1, OA)
      11. 5.12.11 Transimpedance Amplifier (TIA)
        1. Table 5-25 TIA0
      12. 5.12.12 FRAM
        1. Table 5-26 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-27 JTAG, Spy-Bi-Wire Interface
        2. Table 5-28 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.11.8  Timers (Timer0_B3, Timer1_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 SAC0
      14. 6.11.14 TIA0
      15. 6.11.15 eCOMP0, SAC0, TIA0, and ADC in SOC Interconnection
      16. 6.11.16 Embedded Emulation Module (EEM)
      17. 6.11.17 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.12.2 Port P2 Input/Output With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8器件和文档支持
    1. 8.1 使用入门
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 社区资源
    7. 8.7 商标
    8. 8.8 静电放电警告
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息
  10. 重要声明
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DATA SHEET

MSP430FR231x 混合信号微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • 嵌入式微控制器
    • 频率高达 16MHz 的 16 位精简指令集计算机 (RISC) 架构
    • 3.6V 至 1.8V 的宽电源电压范围（最低电源电压受限于 SVS 电平，请参阅 SVS 规格）
  • 经优化的低功耗模式（3V 时）
    • 激活模式：126µA/MHz
    • 待机模式：实时时钟 (RTC) 计数器（LPM3.5，采用 32768Hz 晶振）0.71µA
    • 关断模式 (LPM4.5)：32nA（无 SVS）
  • 高性能模拟
    • 跨阻放大器 (TIA) (1)
      • 电流至电压转换
      • 半轨输入
      • 仅针对 TSSOP16 封装，将低泄漏负输入降至 5pA
      • 轨至轨输出
      • 多个输入信号选项
      • 可配置的高功率和低功率模式
    • 8 通道 10 位模数转换器 (ADC)
      • 1.5V 的内部基准电压
      • 采样与保持 200ksps
    • 增强型比较器 (eCOMP)
      • 集成 6 位数模转换器 (DAC) 作为基准电压
      • 可编程迟滞
      • 可配置的高功率和低功率模式
    • 智能模拟组合 (SAC-L1)
      • 支持通用运算放大器
      • 轨至轨输入和输出
      • 多个输入信号选项
      • 可配置的高功率和低功率模式
      • 1. 以前，跨阻放大器在描述性文字、引脚名称和电阻器名称中的缩写都是 TRI。现在将所有描述性文字中的缩写改成了 TIA，但引脚名称和电阻器名称仍然使用 TRI。
  • 低功耗铁电 RAM (FRAM)
    • 非易失性存储器容量高达 3.75KB
    • 内置错误修正码 (ECC)
    • 可配置的写保护
    • 对程序、常量和存储的统一存储
    • 耐写次数达 1015 次
    • 抗辐射和非磁性
  • 智能数字外设
    • 红外调制逻辑
    • 两个 16 位计时器，每个计时器有 3 个捕捉/比较寄存器 (Timer_B3)
    • 一个仅用作计数器的 16 位 RTC 计数器
    • 16 位循环冗余校验器 (CRC)
  • 增强型串行通信
    • 增强型 USCI A (eUSCI_A) 支持 UART、IrDA 和 SPI
    • 增强型 USCI B (eUSCI_B) 支持 SPI 和 I2C，并提供重映射功能（请参阅信号说明）
  • 时钟系统 (CS)
    • 片上 32kHz RC 振荡器 (REFO)
    • 带有锁频环 (FLL) 的片上 16MHz 数控振荡器 (DCO)
      • 室温下的精度为 ±1%（具有片上基准）
    • 片上超低频 10kHz 振荡器 (VLO)
    • 片上高频调制振荡器 (MODOSC)
    • 外部 32kHz 晶振 (LFXT)
    • 外部高频晶体振荡器，频率高达 16MHz (HFXT)
    • 可编程 MCLK 预分频器（1 至 128）
    • 通过可编程预分频器（1、2、4 或 8）从 MCLK 获得的 SMCLK
  • 通用输入/输出和引脚功能
    • 20 引脚封装有 16 个 I/O
    • 12 个中断引脚（8 个 P1 引脚和 4 个 P2 引脚）可将 MCU 从 LPM 唤醒
    • 所有 I/O 均为电容式触控 I/O
  • 开发工具和软件
    • LaunchPad™开发套件 (MSP‑EXP430FR2311)
    • 目标开发板 (MSP‑TS430PW20)
  • 系列成员（另请参阅器件比较）
    • MSP430FR2311：3.75KB 程序 FRAM 和 1KB RAM
    • MSP430FR2310：2KB 程序 FRAM 和 1KB RAM
  • 封装选项
    • 20 引脚 TSSOP (PW20)
    • 16 引脚 TSSOP (PW16)
    • 16 引脚 VQFN (RGY16)

1.2 应用

  • 烟雾探测器
  • 移动电源
  • 便携式保健和健身设备
  • 电源监控
  • 个人电子产品

1.3 说明

MSP430FR231x FRAM 微控制器 (MCU) 属于 MSP430™MCU 超值系列检测系列中的一员。这些器件集成了可配置的低泄漏跨阻放大器 (TIA) 和通用运算放大器。MCU 具有功能强大的 16 位 RISC CPU、16 位寄存器和常数发生器，有助于实现最大编码效率。数控振荡器 (DCO) 还可以让器件在不到 10µs 的时间内从低功耗模式唤醒至活动模式。这些 MCU 的功能集 非常适合从 烟雾探测器到便携式医疗和健身配件等多种应用。

超低功耗的 MSP430FR231x MCU 系列包含多种器件，其中配备了嵌入式非易失性 FRAM 和不同的外设集，适用于各种检测和测量 应用中的数字输入 D 类音频放大器。该架构、FRAM 和外设与多种低功耗模式相结合，专为在便携式无线感测应用 中延长电池使用寿命而进行了优化中的数字输入 D 类音频放大器。FRAM 是一种非易失性存储器技术，它将 SRAM 的速度、灵活性和耐用性与闪存的稳定性和可靠性相结合，并且总功耗更低。

MSP430FR231x MCU 由一个由各种软、硬件资源组成的生态系统提供支持，并配套提供有参考设计和代码示例，可帮助您快速开展设计。开发套件包括 MSP‑EXP430FR2311LaunchPad™开发套件和 MSP‑TS430PW20 20 引脚目标开发板。TI 提供免费的 MSP430Ware™ 软件，可作为Code Composer Studio™ IDE 台式机和云版本（位于 TI Resource Explorer）的组件。MSP430 MCU 还通过E2E™ 社区论坛提供广泛的在线配套资料、培训和在线支持。

有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。

器件信息(1)

器件型号 封装 封装尺寸(2)
MSP430FR2311IPW20 TSSOP (20) 6.5mm × 4.4mm
MSP430FR2310IPW20
MSP430FR2311IPW16 TSSOP (16) 5mm × 4.4mm
MSP430FR2310IPW16
MSP430FR2311IRGY VQFN (16) 4mm × 3.5mm
MSP430FR2310IRGY
(1) 要获得最新的产品、封装和订购信息，请参见封装选项附录（Section 9），或者访问德州仪器 (TI) 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（Section 9中）。

CAUTION

系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430™ 系统级 ESD 注意事项》。

1.4 功能框图

Figure 1-1 所示为功能框图。

MSP430FR2311 MSP430FR2310 msp430fr2311-functional-block-diagram.gifFigure 1-1 MSP430FR231x 功能方框图
  • MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为 4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
  • P1 的 8 个引脚和 P2 的 4 个引脚均具备引脚中断功能，可将 MCU 从所有低功耗模式 (LPM) 唤醒（包括 LPM4、LPM3.5 和 LPM4.5）。
  • 每个 Timer_B3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周期时序和生成中断。
  • 在 LPM3.5 模式下，RTC 计数器与备用存储器可继续工作，而其余外设停止工作。
  • 所有通用 I/O 均可配置为电容式触控 I/O。

2 修订历史记录

从修订版本 D 更改为修订版本 E

Changes from August 29, 2018 to December 9, 2019

  • Updated Section 3.1, Related ProductsGo
  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Corrected "SVS Enabled" test condition on Figure 5-2, LPM3.5 Supply Current vs TemperatureGo
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the parameter symbol from RI to RI,MUX in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Corrected the test conditions for the RI,MUX parameter in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added RI,Misc TYP value of 34 kΩ in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added formula for RI in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Corrected bitfield from RTCCLK to RTCCKSEL in Table 6-8, Clock DistributionGo
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 6.11.8, Timers (Timer0_B3, Timer1_B3) , in the description that starts "The interconnection of Timer0_B3 and ..."Go
  • Added P1SELC information in Table 6-31, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 6-31, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added note to "ADC calibration" in Table 6-46, Device DescriptorsGo

Changes from September 12, 2017 to August 28, 2018

  • Updated Section 3.1, Related ProductsGo
  • Added note to VSVSH- and VSVSH+ parameters in Table 5-1, PMM, SVS and BORGo
  • Corrected ADCINCHx column heading in Table 6-16, ADC Channel ConnectionsGo
  • 更新了Section 8.2器件命名规则 中的文本和图Go

Changes from June 1, 2016 to September 11, 2017

  • 更正了“关断模式 (LPM4.5)” 特性 列表项中的电流Go
  • 根据测试数据，低泄漏输入从 50pA 降为 5pAGo
  • Added Section 3.1, Related ProductsGo
  • Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-21, ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division)Go
  • Changed the entries for eUSCI_A0 and eUSCI_B0 in the LPM3 column from Off to Optional in Table 6-1, Operating ModesGo
  • Added the sentence that begins "This device supports blank device detection..." in Section 6.6, Bootloader (BSL)Go
  • Added the note "Controlled by the RTCCLK bit in the SYSCFG2 register" on Table 6-8, Clock DistributionGo
  • Added Figure 6-1, Clock Distribution Block DiagramGo
  • Added Figure 6-2, Timer_B ConnectionsGo
  • Removed SYSBERRIV register (not supported) in Table 6-26, SYS RegistersGo
  • Changed from "If the RST/NMI pin is unused...with a 2.2-nF pulldown capacitor" to "If the RST/NMI pin is unused...with a 10-nF pulldown capacitor"Go

Changes from March 30, 2016 to May 31, 2016

  • 将器件状态从“产品预发布”更改为“生产数据” Go
  • Changed the value of fXT1 in the table note that starts "Low-power mode 4, VLO,..."Go
  • Added Test Conditions to module Timer_B in Section 5.10, Typical Characteristics – Current Consumption Per ModuleGo
  • Added "16 MHz" to the parameter description of tFLL, lock in Table 5-5, DCO FLLGo
  • Removed ±3℃ from calibration temperatures in the table note that starts "The device descriptor structure contains calibration values..."Go
  • Changed the unit on the ENI parameter in Table 5-24, SAC0 (SAC-L1, OA)Go
  • Changed the unit on the ENI parameter in Table 5-25, TIA0Go

Changes from February 23, 2016 to March 29, 2016

  • 已将整篇文档中 TIA 模块的名称由“TRI0”更改为“TIA0”Go
  • Changed TYP values for the IAM, FRAM(0%) parameter in Section 5.4, Active Mode Supply Current Into VCC Excluding External CurrentGo
  • Changed MAX values of the tVALID,SO parameter in Table 5-18, eUSCI (SPI Slave Mode) Switching CharacteristicsGo
  • Changed the TYP value of the CMRR parameter with Test Conditions of "TRIPM = 0" from 70 dB to 80 dB in Table 5-25, TIA0Go
  • Changed the TYP value of the PSRR parameter with Test Conditions of "TRIPM = 0" from 70 dB to 80 dB in Table 5-25, TIA0Go
  • 已将旧版中的开发工具支持部分替换为Section 8.3，工具和软件Go

3 Device Comparison

Table 3-1 summarizes the features of the available family members.

Table 3-1 Device Comparison(1)(2)

DEVICE PROGRAM FRAM (KB) SRAM (Bytes) TB0, TB1 eUSCI_A eUSCI_B 10-BIT ADC CHANNELS SAC0 (OA) TIA0 eCOMP0 I/O PACKAGE
MSP430FR2311IPW20 3.75 1024 3 CCR(3) 1 1 8 1 1 1 16 20 PW (TSSOP)
MSP430FR2310IPW20 2 1024 3 CCR(3) 1 1 8 1 1 1 16 20 PW (TSSOP)
MSP430FR2311IPW16 3.75 1024 3 CCR(3)(4) 1 1 8 1 1 1 11 16 PW (TSSOP)
MSP430FR2310IPW16 2 1024 3 CCR(3)(4) 1 1 8 1 1 1 11 16 PW (TSSOP)
MSP430FR2311IRGY 3.75 1024 3 CCR(3) 1 1 8 1 1 1 12 16 RGY (VQFN)
MSP430FR2310IRGY 2 1024 3 CCR(3) 1 1 8 1 1 1 12 16 RGY (VQFN)
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs.
(4) TB1 provides only one external connection (TB1.1) on this package.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement MCUs

One platform. One ecosystem. Endless possibilities.

Companion products for MSP430FR2311

Review products that are frequently purchased or used with this product.

Reference designs for MSP430FR2311

Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors

 
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