TIDUEM8B March   2019  – February 2021

 

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2.3.2.1.1 Clock

The MSP432 MCU is configured to have its CPU clock (MCLK) set at 48 MHz and its subsystem master clock (SMCLK) set to 8.192 MHz. The clock source for MCLK is the internal DCO of the MSP432 MCU, which is configured for a frequency of 48 MHz. The clock source for SMCLK is an external 16.384-MHz crystal, which is internally divided by 2 to create the 8.192-MHz SMCLK frequency. An external 32.768-kHz crystal is used as the clock source for the auxiliary clock (ACLK) of the device. This ACLK clock is set to a frequency of 32.768 kHz.