TIDT434 February   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Required Equipment
    3. 1.3 Dimensions
    4. 1.4 Test Setup
  6. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Efficiency Data
    3. 2.3 Thermal Images
    4. 2.4 Bode Plots
  7. 3Waveforms
    1. 3.1 Switching
    2. 3.2 Output Voltage Ripple
    3. 3.3 Short-Circuit Protection
    4. 3.4 Load Transients
    5. 3.5 Start-up Sequence

3.1 Switching

The maximum voltage stress on the drain of the low-side FETs (Q2 and Q3) occurs with 150V input and 10A load. This was recorded as 170Vpk, as shown in Figure 3-1 and Figure 3-2.

PMP23552 Maximum Voltage Stress, 150VIN, 10A LoadFigure 3-1 Maximum Voltage Stress, 150VIN, 10A Load
PMP23552 Switch Node, 150VIN, 10A LoadFigure 3-2 Switch Node, 150VIN, 10A Load