TIDT417 November   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Required Equipment
    3. 1.3 Considerations
    4. 1.4 Dimensions
    5. 1.5 Test Setup
  6. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Efficiency Data
    3. 2.3 Thermal Images
  7. 3Waveforms
    1. 3.1 Switching
    2. 3.2 Output Voltage Ripple
    3. 3.3 Load Transients
    4. 3.4 Start-up Sequence

2.1 Efficiency Graphs

Figure 2-1 shows the system efficiency from VBUS to VSYS with charge disabled. There was no battery connected to the VBAT terminal. VSYS is equal to 3.75V.

PMP23456 System Efficiency Graph - Charge Disabled Figure 2-1 System Efficiency Graph - Charge Disabled

Charge efficiency is shown in Figure 2-2, from VBUS to VBAT with charge enabled. A 1mF capacitor with an e-load set to constant voltage mode at 3.8V was used to simulate a battery for these measurements.

PMP23456 Charge Efficiency Graph - Charge Enabled Figure 2-2 Charge Efficiency Graph - Charge Enabled