SWRZ097D April   2020  – November 2022 AWR6843

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#26
    3.     MSS#27
    4.     MSS#28
    5.     MSS#29
    6.     MSS#30
    7.     MSS#31
    8.     MSS#32
    9.     MSS#33
    10.     MSS#34
    11.     MSS#36
    12.     MSS#37B
    13.     MSS#38A
    14.     MSS#39
    15.     MSS#40
    16.     MSS#41
    17.     MSS#42A
    18.     MSS#43A
    19.     MSS#44A
    20.     MSS#45
    21. 6.1 MSS#50
    22. 6.2 MSS#51
    23.     ANA#11B
    24. 6.3 ANA#12A
    25.     ANA#13B
    26.     ANA#14
    27.     ANA#15
    28.     ANA#16
    29.     ANA#17A
    30.     ANA#18B
    31.     ANA#19
    32.     ANA#20
    33.     ANA#21
    34.     ANA#22A
    35.     ANA#27A
  7. 7Trademarks
    1.     Revision History

MSS#51

Spurious toggle on nERROR OUT signal during powerup due to undefined state in ESM block

Revision(s) Affected:

AWR6843 ES 1.0 and AWR6843 ES2.0

Description:

When the mmWave device powers up (nReset is released), the internal state machine starts on internal RC oscillator clock before the 40MHz clock is available.

Inside the ESM module (Error Signaling Module), at least 3 cycles of RCOSC CLK cycles are needed to clear the internal states because the Flip Flops (FFs) are non-resettable.

In silicon, the ESM reset might get released before these three RCOSC CLK cycles and at that moment an undefined state of nError out flip flop could get latched. This could be either 0 or 1 since its undefined at that point. Once an error value gets latched, it would be retained until the software clears it. The bootloader then boots up and initializes the ESM block, which then clears the error. Hence, the nError out goes low for about 13msec after the power up, until it is initialized by the bootloader.

Workaround(s):

  1. The Host processor can ignore the nERROR OUT status until the device has fully booted up i.e. until the Host IRQ is raised and the mmWave device is ready to receive the command from the host processor over the SPI interface.
  2. The Host processor could also put a timer from the nRESET release to ensure the nERROR OUT does not remain low beyond a certain time after nRESET release. For example, a 25 msec timer after the nReset release. By this time, the bootloader should have ideally cleared the ESM block and nERROR OUT should go high. If the nERROR OUT still remains low post the timer, then it could indicate a real fault.