SWRZ097D April   2020  – November 2022 AWR6843

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#26
    3.     MSS#27
    4.     MSS#28
    5.     MSS#29
    6.     MSS#30
    7.     MSS#31
    8.     MSS#32
    9.     MSS#33
    10.     MSS#34
    11.     MSS#36
    12.     MSS#37B
    13.     MSS#38A
    14.     MSS#39
    15.     MSS#40
    16.     MSS#41
    17.     MSS#42A
    18.     MSS#43A
    19.     MSS#44A
    20.     MSS#45
    21. 6.1 MSS#50
    22. 6.2 MSS#51
    23.     ANA#11B
    24. 6.3 ANA#12A
    25.     ANA#13B
    26.     ANA#14
    27.     ANA#15
    28.     ANA#16
    29.     ANA#17A
    30.     ANA#18B
    31.     ANA#19
    32.     ANA#20
    33.     ANA#21
    34.     ANA#22A
    35.     ANA#27A
  7. 7Trademarks
    1.     Revision History

MSS#30

MibSPI RX RAM RXEMPTY bit Does Not Get Cleared After Reading

Revision(s) Affected:

AWR6843 ES2.0

Description:

The RXEMPTY flag may not be auto-cleared after a CPU or DMA read when the following conditions are met:

  • The TXFULL flag of the latest buffer that the sequencer read out of transmit RAM for the currently active transfer group is 0,
  • A higher-priority transfer group interrupts the current transfer group and the sequencer starts to read the first buffer of the new transfer group from the transmit RAM, and
  • Simultaneously, the Host (CPU/DMA) is reading out a receive RAM location that contains valid received data from the previous transfers.

Workaround(s):

If at all possible, avoid transfer groups interrupting one another.

If dummy buffers are used in lower-priority transfer groups, select the appropriate "BUFMODE" for them (like, SKIP/DISABLED) unless, there is a specific need to use the "SUSPEND" mode.