SWRZ097D April   2020  – November 2022 AWR6843

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#26
    3.     MSS#27
    4.     MSS#28
    5.     MSS#29
    6.     MSS#30
    7.     MSS#31
    8.     MSS#32
    9.     MSS#33
    10.     MSS#34
    11.     MSS#36
    12.     MSS#37B
    13.     MSS#38A
    14.     MSS#39
    15.     MSS#40
    16.     MSS#41
    17.     MSS#42A
    18.     MSS#43A
    19.     MSS#44A
    20.     MSS#45
    21. 6.1 MSS#50
    22. 6.2 MSS#51
    23.     ANA#11B
    24. 6.3 ANA#12A
    25.     ANA#13B
    26.     ANA#14
    27.     ANA#15
    28.     ANA#16
    29.     ANA#17A
    30.     ANA#18B
    31.     ANA#19
    32.     ANA#20
    33.     ANA#21
    34.     ANA#22A
    35.     ANA#27A
  7. 7Trademarks
    1.     Revision History

MSS#42A

DSP L2 memory initialisation can reoccur on execution DSP self test (STC) OR DSP Power cycling execution by application.

Revision(s) Affected:

AWR6843 ES 1.0 and AWR6843 ES2.0

Description:

MSS Boot ROM Powers on DSP, Performs a Memory Initialisation of DSP L2 and downloads the program code to L2 memory. If the user application executes the STC or DSP power cycle, memory init is triggered again, hence erasing the L2 memory contents.

Workaround(s):

The workaround for Mem init would be to perform a Dummy mem init to reset a latch within the IP while keeping the destination domain in reset. This can be done by the application using the below sequence before running STC or DSP power cycling:

  1. Set the GEM_CLK_EN_BYPASS_CTRL bit in the TOPRCM-> GEMPWRSMCFG2 register Bit 9 as ‘1’.
  2. Set the GEM_GRSTN_GATE_BYPASS_CTRL bit in the TOPRCM-> GEMPWRSMCFG1 Bit 9 register as ‘1’.
  3. Set the GEM_CLK_EN_BYPASS_CTRL bit in the TOPRCM-> GEMPWRSMCFG1 Bit 7 register as ‘1’.
  4. Write a value of 0xFFFF in , DSS_REG ->L2MEMINITCFG1 register.
  5. Write a value of 0xF in , DSS_REG ->L2MEMINITCFG2 register
  6. Write a value of 0x0 in TOPRCM-> GEMPWRSMCFG1-> PWRSMOUTBYPCTRL register.