SWRZ097D April 2020 – November 2022 AWR6843
| Advisory Number | Advisory Title | AWR6843 |
|---|---|---|
| ES2.0 | ||
| Main Subsystem | ||
| MSS#25 | Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset Occurs | X |
| MSS#26 | DMA Requests Lost During Suspend Mode | X |
| MSS#27 | MibSPI in Slave Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1 | X |
| MSS#28 | A Data Length Error is Generated Repeatedly in Slave Mode When IO Loopback is Enabled | X |
| MSS#29 | Spurious RX DMA REQ From a Slave Mode MibSPI | X |
| MSS#30 | MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After Reading | X |
| MSS#31 | CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space | X |
| MSS#32 | DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A Packet | X |
| MSS#33 | MibSPI RAM ECC is Not Read Correctly in DIAG Mode | X |
| MSS#34 | HS Device Does Not Reboot Successfully on Warm Reset Getting Triggered by Watchdog Expiry | X |
| MSS#36 | DMA Read From an Unimplemented Address Space is not Reported as a BUS Error | X |
| MSS#37B | DCC Module Frequency Comparison can Report Erroneous Results | X |
| MSS#38A | GPIO Glitch During Power-Up | X |
| MSS#39 | The State of the MSS DMA is Left Pending and Uncleared on Any DMA MPU fault | X |
| MSS#40 | Any EDMA Transfer that Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result in Data Corruption Without Any Notification of Error From the SoC | X |
| MSS#41 | Issuing WARM_RESET can Cause Bootloader Failure Which Results in Failure to Load the Application From Serial Flash | X |
| MSS#42A | DSP L2 memory initialisation can reoccur on execution DSP self test (STC) OR DSP Power cycling execution by application. | X |
| MSS#43A | Read-data From Internal Registers of PCR Is Not Reliable. Shared PCS Region Protection is Also Not Supported | X |
| MSS#44A | SYNC IN input pulse wider than 4usec can cause a FRC lockstep error | X |
| MSS#45 | Bootup Failure During the Serial Flash Busy State | X |
| MSS#50 | Occasional EDMA self-test failures | X |
| MSS#51 | Spurious toggle on nERROR OUT signal during powerup due to undefined state in ESM block. | X |
| Analog / Millimeter Wave | ||
| ANA#11B | TX, RX Calibrations Sensitive to Large External Interference | X |
| Section 6.3 | Second Harmonic (HD2) Present in the Receiver | X |
| ANA#13B | Phase Mismatch Variation Across Temperature in TX3/TX1 and TX3/TX2 Combinations are higher than that of TX2/TX1 Combination | X |
| ANA#14 | Doppler Spurs Observed for Narrow Chirps | X |
| ANA#15 | Excessive TX-RX Coupling or Reflection can Lead to Saturated RX Output | X |
| ANA#16 | LVDS Coupling to Clock System | X |
| ANA#17A | On-Board Supply Ringing Induced Spur | X |
| ANA#18B | Spurs Caused due to Digital Activity Coupling to XTAL | X |
| ANA#19 | Bandgap Decoupling Capacitor On-Board | X |
| ANA#20 | Occasional Failures Observed During Calibration of the Radar Subsystem | X |
| Section 6.4 | Out of Band Radiated Spectral Emission | X |
| ANA#22A | Overshoot and Undershoot During Inter-Chirp When Dynamic-Power Saving is Disabled | X |
| ANA#27A | Digital Temperature Sensor Readings Differ From Analog Temperature Sensors | X |