SWRZ092B April 2021 – March 2022 IWR6843AOP
| ADVISORY NUMBER |
ADVISORY TITLE | IWR6843AOP | |
|---|---|---|---|
| ES1.0 | ES2.0 | ||
| Main Subsystem | |||
| MSS#03 | Incorrect Handling of “Saturation” in FFT Hardware Accelerator’s Statistics Block | X | |
| MSS#10 | Partial Write After a Full Data Width Write Fails to Mailbox Memory if ECC is Enabled | X | |
| MSS#11 | Clock Monitoring Logic Core Clock Comparator (CCCB) for CPU Clock Cannot be Used | X | |
| MSS#12 | MCAN Filter Event Interrupt not Connected to DMA | X | |
| MSS#13 | Incorrect Read from FFT Hardware Accelerator After Complex Multiplication Operation | X | |
| MSS#14 | Asynchronous Assertion of SoC Warm Reset may not Work Reliably When Device Operating on PLL Clock | X | |
| MSS#16 | Delay Time, ETM Trace Clock to ETM Data Valid does not Meet Datasheet Specification | X | |
| MSS#17 |
Invalid Pre-fetch from MSS CR4 Processor (due to Speculative Read Operation from Tightly Coupled Memory Instance) Leads to Generation of MSS_ESM Group 3 Channel 7: MSS_TCMA_FATAL_ERR | X | |
| MSS#18(1) | Core Compare Module (CCM-R4F) may Cause nERROR Toggle After First Reset De-assertion Subsequent to Power Application | X | |
| MSS#19 | DMA Read from Unimplemented Address Space may Result in DMA Hang Scenario | X | |
| MSS#20 | Radar Frame Stuck due to Missing Synchronizer Logic in Hardware | X | |
| MSS#21 | Issue with HWA Input Formatter 16 bit Real Signed Format | X | |
| MSS#22 | CAN-FD: Message Transmitted With Wrong Arbitration and Control Fields | X | |
| MSS#23 | HWA Read Registers Cannot be Read Reliably When the HWA is Executing a ParamSet Instruction | X | |
| MSS#24 | Limitation With Peak Grouping Feature in Hardware Accelerator | X | |
| MSS#25 | Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset Occurs | X | X |
| MSS#26 | DMA Requests Lost During Suspend Mode | X | X |
| MSS#27 | MibSPI in Slave Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1 | X | X |
| MSS#28 | A Data Length Error is Generated Repeatedly in Slave Mode When IO Loopback is Enabled | X | X |
| MSS#29 | Spurious RX DMA REQ From a Peripheral Mode MibSPI | X | X |
| MSS#30 | MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After Reading | X | X |
| MSS#31 | CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space | X | X |
| MSS#32 | DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A Packet | X | X |
| MSS#33 | MibSPI RAM ECC is Not Read Correctly in DIAG Mode | X | X |
| MSS#34 | HS Device Does Not Reboot Successfully on Warm Reset Getting Triggered by Watchdog Expiry | X | X |
| MSS#35 | EDMA TPTC Generates an Incorrect Address on the Read Interface, Causing one or More Data Integrity Failures, Hangs, or Extra Reads | X | |
| MSS#36 | DMA Read From an Unimplemented Address Space is not Reported as a BUS Error | X | |
| MSS#37B | DCC Module Frequency Comparison can Report Erroneous Results | X | X |
| MSS#38A | GPIO Glitch During Power-Up | X | X |
| MSS#39 | The State of the MSS DMA is Left Pending and Uncleared on Any DMA MPU Fault | X | X |
| MSS#40 | Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC | X | X |
| MSS#41 | Issuing WARM_RESET can Cause Bootloader Failure Which Results in Failure to Load the Application From Serial Flash | X | X |
| MSS#42A | DSP L2 Memory Initialisation can Reoccur on Execution DSP Self Test (STC) OR DSP Power Cycling Execution by Application. | X | X |
| MSS#43A | Read-Data from Internal Registers of PCR is Not Reliable. Shared PCS Region Protection is Also Not Supported | X | X |
| MSS#44A | SYNC IN Input Pulse Wider Than 4usec can Cause a FRC Lockstep Error | X | X |
| MSS#45 | Bootup Failure During the Serial Flash Busy State | X | X |
| MSS#50 | Occasional EDMA self-test failures | X | X |
| MSS#51 | Spurious toggle on nERROR OUT signal during powerup due to undefined state in ESM block. | X | X |
| Analog / Millimeter Wave | |||
| ANA#11B | TX, RX Gain Calibrations Sensitive to Large External Interference | X | X |
| ANA#12A | Second Harmonic (HD2) is Present When Receiver is Tested Standalone Using CW Input | X | X |
| ANA#13B | Phase Mismatch Variation Across Temperature in TX3/TX1 and TX3/TX2 Combinations are higher than that of TX2/TX1 Combination | X | X |
| ANA#14 | Doppler Spur Observed for Narrow Chirps Spanning 59.4 GHz and 62.1 GHz | X | X |
| ANA#16 | LVDS Coupling to Clock System | X | X |
| ANA#17A | On-Board Supply Ringing Induced Spur | X | X |
| ANA#18B | Spurs Caused due to Digital Activity Coupling to XTAL | X | X |
| ANA#19 | Bandgap Decoupling Capacitor On-Board | X | X |
| ANA#20 | Occasional Failures Observed During Calibration of the Radar Subsystem | X | X |
| ANA#22A | Overshoot and Undershoot During Inter-Chirp Idle Time | X | X |
| ANA#27A | Digital Temperature Sensor Readings Differ From Analog Temperature Sensors | X | X |
| ANA#30 | Inter-Channel Mismatch Variation Across Angle of Arrival | X | X |
| ANA#31 | Increase in Rx Effective Isotropic Noise Figure when Tx Chains are Turned ON | X | X |
| DSP Subsystem | |||
| DSS#01 | Access to L3 Region Above Allocated Region may Result in Double Bit ECC Error if ECC is Enabled | X | |
| DSS#02 | L1P Parity Error not Connected to ESM | X | |
| DSS#03 | Different Number of Chirps in ADC Buffer's Ping and Pong Memory is not Supported | X | |
| DSS#05 | Byte Writes not Supported to L3 If ECC is Enabled | X | |
| DSS#07 | Temperature Sensor Located Near DSP not Working | X | |
| PACKAGE | |||
| PACKAGE#01 | Mechanical Package Change from ES1.0 to ES2.0 | X | |
| PACKAGE#02 | Surface Wave Artefact from PCB | X | X |