Revisions Affected

IWR6843AOP ES1.0, ES2.0

Details

When the mmWave device powers up (nReset is released), the internal state machine starts on internal RC oscillator clock before the 40MHz clock is available.

Inside the ESM module (Error Signaling Module), at least 3 cycles of RCOSC CLK cycles are needed to clear the internal states because the Flip Flops (FFs) are non-resettable.

In silicon, the ESM reset might get released before these three RCOSC CLK cycles and at that moment an undefined state of nError out flip flop could get latched. This could be either 0 or 1 since its undefined at that point. Once an error value gets latched, it would be retained until the software clears it. The bootloader then boots up and initializes the ESM block, which then clears the error. Hence, the nError out goes low for about 13msec after the power up, until it is initialized by the bootloader.

Workaround

1. The Host processor can ignore the nERROR OUT status until the device has fully booted up i.e. until the Host IRQ is raised and the mmWave device is ready to receive the command from the host processor over the SPI interface.
2. The Host processor could also put a timer from the nRESET release to ensure the nERROR OUT does not remain low beyond a certain time after nRESET release. For example, a 25 msec timer after the nReset release. By this time, the bootloader should have ideally cleared the ESM block and nERROR OUT should go high. If the nERROR OUT still remains low post the timer, then it could indicate a real fault.