SWRZ074C May   2017  – May 2021 IWR1443

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
    2. 4.2 Identification
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#01
    2.     MSS#03A
    3.     MSS#04A
    4.     MSS#05A
    5.     MSS#06
    6.     MSS#07A
    7.     MSS#08
    8.     MSS#09
    9.     MSS#13
    10.     MSS#14
    11.     MSS#15
    12.     MSS#19
    13.     MSS#20
    14.     MSS#21A
    15.     MSS#22
    16.     MSS#23
    17.     MSS#24
    18.     MSS#25
    19.     MSS#26
    20.     MSS#27
    21.     MSS#28
    22.     MSS#29
    23.     MSS#30
    24.     MSS#31
    25.     MSS#32
    26.     MSS#33
    27.     MSS#35
    28.     MSS#37B
    29.     MSS#38A
    30.     MSS#39
    31.     MSS#40
    32.     MSS#43A
    33.     MSS#44
    34.     MSS#45
    35.     ANA#01
    36.     ANA#02
    37.     ANA#03
    38.     ANA#04
    39.     ANA#06
    40.     ANA#07
    41.     ANA#08A
    42.     ANA#10A
    43.     ANA#11A
    44.     ANA#12A
    45.     ANA#13B
    46.     ANA#15
    47.     ANA#16
    48.     ANA#17A
    49.     ANA#18B
    50.     ANA#20
    51.     ANA#21A
    52.     ANA#22A
    53.     ANA#24A
    54.     ANA#27
  7. 7Trademarks
  8. 8Revision History

MSS#37B

DCC Module Frequency Comparison can Report Erroneous Results

Revision(s) Affected:

IWR1443 ES1.0, IWR1443 ES2.0, and IWR1443 ES3.0

Description:

The Dual-clock Comparator module, which is used to monitor a clock frequency while comparing with a known clock reference, could stop earlier than expected, and, thus, indicating the measured clock frequency to be lower. This is due to a clock domain crossing issue causing a preset to the error detection logic to get triggered.

Workaround(s):

Multiple measurements can be taken for the same clock pairs and abnormal frequencies reported can be ignored

Application code, where possible, could compare the clocks using an alternate clock comparator module (CCC).