Figure 2-2 shows the coder implemented in the DSSS modulation. A convolutional encoder is defined by its rate, its constraint-length K (number of stages in the encoding shift register) and the connections between its internal states. The convolutional encoder used in this case has K = 4 and only supports ½ rate, that is, for every input bit, the encoder produces two output bits.

The connections between internal states are a fundamental way of defining the code. The implemented encoder is based on non-systematic, non-recursive convolutional code.

The black dots in Figure 2-2 represent logic XOR operations. The two output bits (a₀, a₁) from the encoder are serialized in a way that a₀ is transmitted first and a₁ is transmitted last.