SPRZ575 March   2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2120
      5.      i2137
      6.      i2189
      7.      i2190
      8.      i2196
      9.      i2199
      10.      i2208
      11.      i2242
      12.      i2243
      13.      i2249
      14.      i2253
      15.      i2278
      16.      i2279
      17.      i2310
      18.      i2311
      19.      i2312
      20.      i2326
      21.      i2351
      22.      i2362
      23.      i2366
      24.      i2372
      25.      i2383
      26.      i2399
      27.      i2401
      28.      i2407
      29.      i2409
      30.      i2410
  5.   Trademarks
  6. 4Revision History

i2243

PCIe: Timing requirement for disabling output refclk during L1.2 substate is not met

Details

PCIe base specification requires Refclk to reach idle electrical state within 100ns of CLKREQ# deassertion when entering L1.2 substate (please refer TL1O_REFCLK_OFF parameter).

This timing requirement cannot be met when sourcing Refclk from the device since hardware does not automatically gate Refclk. Refclk gating has to be performed by software by writing to PHY_EN_REFCLK field in SERDES_RST register.

As a result, Refclk cannot be gated in L1.2 substate. Generally, allowing Refclk to run in L1.2 substate is not expected to cause any functional issues. However, if gating Refclk within 100ns is required by the system, L1.2 substate cannot be supported.

Workaround

Use an external Refclk generator to supply the PCIe reference clock