SPRZ408D June   2014  – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Device and Development Support Tool Nomenclature
    2. 1.2 Revision Identification
  3. 2All Errata Listed With Silicon Revision Number
  4. 3Usage Notes and Known Design Exceptions to Functional Specifications
    1. 3.1 Usage Notes
      1. 3.1.1 LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval
      2. 3.1.2 DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode
    2. 3.2 Known Design Exceptions to Functional Specifications
      1. 3.2.1 Advisory List
      2.      Advisory 1
      3.      Advisory 2
      4.      Advisory 3
      5.      Advisory 4
      6.      Advisory 5
      7.      Advisory 6
      8.      Advisory 7
      9.      Advisory 8
      10.      Advisory 9
      11.      Advisory 10
      12.      Advisory 11
      13.      Advisory 12
      14.      Advisory 13
      15.      Advisory 14
      16.      Advisory 15
      17.      Advisory 16
      18.      Advisory 17
      19.      Advisory 19
      20.      Advisory 20
      21.      Advisory 21
      22.      Advisory 22
      23.      Advisory 24
      24.      Advisory 25
      25.      Advisory 26
      26.      Advisory 27
      27.      Advisory 28
      28.      i2223
      29.      i2224
      30.      i912
      31.      i2225
      32.      i2226
  5. 4Revision History

Advisory 11

Asynchronous Bridge Corruption

Revisions Affected

1.1, 1.2

Details

If data is stalled inside an asynchronous bridge because of back pressure, it may be accepted multiple times and create pointer misalignment that corrupts the next transfers on that data path until the system is reset. There is no recovery procedure once the issue is hit because the path remains consistently broken.  The async bridge can be found on the path between MPU to L3 interconnect (to EMIF) and Cortex M3 to L3 interconnect (to EMIF).  This situation can happen only when the idle is initiated by a master request disconnection, which is trigged by software when executing WFI.

Workaround

All the initiators connected through the asynchronous bridge must ensure that data path is properly drained before issuing WFI. This condition is met if one strongly ordered access is performed to the target right before executing the WFI.