SPRZ408D June   2014  – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Device and Development Support Tool Nomenclature
    2. 1.2 Revision Identification
  3. 2All Errata Listed With Silicon Revision Number
  4. 3Usage Notes and Known Design Exceptions to Functional Specifications
    1. 3.1 Usage Notes
      1. 3.1.1 LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval
      2. 3.1.2 DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode
    2. 3.2 Known Design Exceptions to Functional Specifications
      1. 3.2.1 Advisory List
      2.      Advisory 1
      3.      Advisory 2
      4.      Advisory 3
      5.      Advisory 4
      6.      Advisory 5
      7.      Advisory 6
      8.      Advisory 7
      9.      Advisory 8
      10.      Advisory 9
      11.      Advisory 10
      12.      Advisory 11
      13.      Advisory 12
      14.      Advisory 13
      15.      Advisory 14
      16.      Advisory 15
      17.      Advisory 16
      18.      Advisory 17
      19.      Advisory 19
      20.      Advisory 20
      21.      Advisory 21
      22.      Advisory 22
      23.      Advisory 24
      24.      Advisory 25
      25.      Advisory 26
      26.      Advisory 27
      27.      Advisory 28
      28.      i2223
      29.      i2224
      30.      i912
      31.      i2225
      32.      i2226
  5. 4Revision History

2 All Errata Listed With Silicon Revision Number

Advisories are numbered in the order in which they were added to this document. Some advisory numbers may be moved to the next revision and others may have been removed because the design exception was fixed or documented in the device-specific data manual or peripheral user's guide. When items are moved or deleted, the remaining numbers remain the same and are not re-sequenced.

Table 2-1 All Usage Notes
NUMBERTITLESILICON REVISION AFFECTED
1.11.2
Section 3.1.1LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command IntervalXX
Section 3.1.2DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR ModeXX
Table 2-2 All Design Exceptions to Functional Specifications
NUMBERTITLESILICON REVISION AFFECTED
1.11.2
Advisory 1UART: Extra Assertion of FIFO Transmit DMA Request, UARTi_DMA_TXXX
Advisory 2ROM: USB Host Boot is UnsupportedX
Advisory 3ROM: USB Client Boot is UnsupportedX
Advisory 4ROM: RGMII Clocking Register is Not Configured Properly at OPP50X
Advisory 5ROM: Trace Vector Does Not Reflect that TFTP Transfer Has Been InitiatedX
Advisory 6ROM: Booting from Redundant Image in NAND Does Not Work as ExpectedX
Advisory 7ROM: NAND Booting is Slower than ExpectedX
Advisory 8ROM: In NOR Low Latency Boot Mode, Wait Monitoring Will Not WorkX
Advisory 9ROM: NAND ECC May Not Be Chosen Correctly by the ROMX
Advisory 10ROM: Peripheral Boot is Not SupportedX
Advisory 11Asynchronous Bridge CorruptionXX
Advisory 12DebugSS:  Register Identifier Field (MasterID) of Statistics Collector Has a Default Value of 0x0 Instead of the Expected IDXX
Advisory 13DSS:  DSS Smart Standby May Cause Synchronization IssuesXX
Advisory 14DSS: DSS LimitationsXX
Advisory 15ROM: NAND Boot Mode is UnsupportedX
Advisory 16McASP: McASP to EDMA Synchronization Level Event Can Be LostXX
Advisory 17DebugSS: DebugSS Does Not Acknowledge Idle RequestXX
Advisory 19TSC_ADC: False Pen-up InterruptsXX
Advisory 20GPTimer: Delay Needed to Read Some GPTimer Registers After WakeupXX
Advisory 21UART: UART0-5 Do Not Acknowledge Idle Request After DMA Has Been EnabledXX
Advisory 22Watchdog Timers: Delay Needed to Read Some WDTimer Registers After WakeupXX
Advisory 24VDD_MPU_MON Not Connected to DieXX
Advisory 25Ethernet Boot: ROM May Select 1-Gbit, Half-Duplex Mode During Auto-negotiation and Fail to BootXX
Advisory 26AutoCMD12 Mode: CMD12 Command is Not Issued on Write Transfer CompletionXX
Advisory 27UART: Spurious UART Interrupts When Using EDMAXX
Advisory 28UART: Transactions to MDR1 Register May Cause Undesired Effect on UART OperationXX
i2223 ROM: Non-muxed Fast NOR boot does not onfigure A26 and A27 X X
i2224 DCAN: RAMINIT_DONE intermittently fails to latch completion X X
i912 QSPI: QSPI register bitfield incorrectly masked when read X X
i2225 Possible underflow condition when using EDMA with UART1, UART2, and UART3 X X
i2226 PRU-ICSS: Burst data transfer between ICSS instances not supported X X